From b1af5b6f675f2f38e2efa351f24441f2ea156bb3 Mon Sep 17 00:00:00 2001 From: Cullen Rhodes Date: Fri, 31 May 2019 08:59:40 +0000 Subject: [PATCH] [AArch64][SVE2] Asm: support SVE2 store instructions Summary: Patch adds support for the following instructions: * STNT1B, STNT1H, STNT1S, STNT1D The specification can be found here: https://developer.arm.com/docs/ddi0602/latest Reviewed By: chill Differential Revision: https://reviews.llvm.org/D62599 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362213 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/AArch64/AArch64SVEInstrInfo.td | 10 +++ lib/Target/AArch64/SVEInstrFormats.td | 37 ++++++++++ test/MC/AArch64/SVE/stnt1b-diagnostics.s | 4 +- test/MC/AArch64/SVE2/stnt1b-diagnostics.s | 82 +++++++++++++++++++++++ test/MC/AArch64/SVE2/stnt1b.s | 80 ++++++++++++++++++++++ test/MC/AArch64/SVE2/stnt1d-diagnostics.s | 82 +++++++++++++++++++++++ test/MC/AArch64/SVE2/stnt1d.s | 44 ++++++++++++ test/MC/AArch64/SVE2/stnt1h-diagnostics.s | 82 +++++++++++++++++++++++ test/MC/AArch64/SVE2/stnt1h.s | 80 ++++++++++++++++++++++ test/MC/AArch64/SVE2/stnt1w-diagnostics.s | 82 +++++++++++++++++++++++ test/MC/AArch64/SVE2/stnt1w.s | 80 ++++++++++++++++++++++ 11 files changed, 661 insertions(+), 2 deletions(-) create mode 100644 test/MC/AArch64/SVE2/stnt1b-diagnostics.s create mode 100644 test/MC/AArch64/SVE2/stnt1b.s create mode 100644 test/MC/AArch64/SVE2/stnt1d-diagnostics.s create mode 100644 test/MC/AArch64/SVE2/stnt1d.s create mode 100644 test/MC/AArch64/SVE2/stnt1h-diagnostics.s create mode 100644 test/MC/AArch64/SVE2/stnt1h.s create mode 100644 test/MC/AArch64/SVE2/stnt1w-diagnostics.s create mode 100644 test/MC/AArch64/SVE2/stnt1w.s diff --git a/lib/Target/AArch64/AArch64SVEInstrInfo.td b/lib/Target/AArch64/AArch64SVEInstrInfo.td index e89dc905415..a7d31cc0c6b 100644 --- a/lib/Target/AArch64/AArch64SVEInstrInfo.td +++ b/lib/Target/AArch64/AArch64SVEInstrInfo.td @@ -1357,6 +1357,16 @@ let Predicates = [HasSVE2] in { defm SRSHR_ZPmI : sve_int_bin_pred_shift_imm_right<0b1100, "srshr">; defm URSHR_ZPmI : sve_int_bin_pred_shift_imm_right<0b1101, "urshr">; defm SQSHLU_ZPmI : sve_int_bin_pred_shift_imm_left< 0b1111, "sqshlu">; + + // Non-temporal contiguous stores (vector + register) + defm STNT1B_ZZR_S : sve2_mem_cstnt_vs<0b001, "stnt1b", Z_s, ZPR32>; + defm STNT1H_ZZR_S : sve2_mem_cstnt_vs<0b011, "stnt1h", Z_s, ZPR32>; + defm STNT1W_ZZR_S : sve2_mem_cstnt_vs<0b101, "stnt1w", Z_s, ZPR32>; + + defm STNT1B_ZZR_D : sve2_mem_cstnt_vs<0b000, "stnt1b", Z_d, ZPR64>; + defm STNT1H_ZZR_D : sve2_mem_cstnt_vs<0b010, "stnt1h", Z_d, ZPR64>; + defm STNT1W_ZZR_D : sve2_mem_cstnt_vs<0b100, "stnt1w", Z_d, ZPR64>; + defm STNT1D_ZZR_D : sve2_mem_cstnt_vs<0b110, "stnt1d", Z_d, ZPR64>; } let Predicates = [HasSVE2AES] in { diff --git a/lib/Target/AArch64/SVEInstrFormats.td b/lib/Target/AArch64/SVEInstrFormats.td index f2299548969..afe845a52e5 100644 --- a/lib/Target/AArch64/SVEInstrFormats.td +++ b/lib/Target/AArch64/SVEInstrFormats.td @@ -3827,6 +3827,43 @@ multiclass sve_mem_cstnt_ss msz, string asm, RegisterOperand listty, (!cast(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm), 0>; } +class sve2_mem_cstnt_vs_base opc, dag iops, string asm, + RegisterOperand VecList> +: I<(outs VecList:$Zt), iops, + asm, "\t$Zt, $Pg, [$Zn, $Rm]", + "", + []>, Sched<[]> { + bits<3> Pg; + bits<5> Rm; + bits<5> Zn; + bits<5> Zt; + let Inst{31-25} = 0b1110010; + let Inst{24-22} = opc; + let Inst{21} = 0b0; + let Inst{20-16} = Rm; + let Inst{15-13} = 0b001; + let Inst{12-10} = Pg; + let Inst{9-5} = Zn; + let Inst{4-0} = Zt; + + let mayStore = 1; +} + +multiclass sve2_mem_cstnt_vs opc, string asm, + RegisterOperand listty, ZPRRegOp zprty> { + def _REAL : sve2_mem_cstnt_vs_base; + + def : InstAlias(NAME # _REAL) zprty:$Zt, PPR3bAny:$Pg, zprty:$Zn, GPR64:$Rm), 0>; + def : InstAlias(NAME # _REAL) zprty:$Zt, PPR3bAny:$Pg, zprty:$Zn, XZR), 0>; + def : InstAlias(NAME # _REAL) listty:$Zt, PPR3bAny:$Pg, zprty:$Zn, GPR64:$Rm), 0>; + def : InstAlias(NAME # _REAL) listty:$Zt, PPR3bAny:$Pg, zprty:$Zn, XZR), 1>; +} + class sve_mem_sst_sv opc, bit xs, bit scaled, string asm, RegisterOperand VecList, RegisterOperand zprext> : I<(outs), (ins VecList:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, zprext:$Zm), diff --git a/test/MC/AArch64/SVE/stnt1b-diagnostics.s b/test/MC/AArch64/SVE/stnt1b-diagnostics.s index 4b7806e5b0e..0d0488d810e 100644 --- a/test/MC/AArch64/SVE/stnt1b-diagnostics.s +++ b/test/MC/AArch64/SVE/stnt1b-diagnostics.s @@ -23,12 +23,12 @@ stnt1b z0.h, p0, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: stnt1b z0.s, p0, [x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK-NEXT: stnt1b z0.s, p0, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: stnt1b z0.d, p0, [x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK-NEXT: stnt1b z0.d, p0, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE2/stnt1b-diagnostics.s b/test/MC/AArch64/SVE2/stnt1b-diagnostics.s new file mode 100644 index 00000000000..dbf30a6cc0f --- /dev/null +++ b/test/MC/AArch64/SVE2/stnt1b-diagnostics.s @@ -0,0 +1,82 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// --------------------------------------------------------------------------// +// Invalid result type. + +stnt1b { z0.b }, p0, [z0.s] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: stnt1b { z0.b }, p0, [z0.s] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +stnt1b { z0.h }, p0, [z0.s] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: stnt1b { z0.h }, p0, [z0.s] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid base vector. + +stnt1b { z0.s }, p0, [z0.b] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: stnt1b { z0.s }, p0, [z0.b] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +stnt1b { z0.d }, p0, [z0.h] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: stnt1b { z0.d }, p0, [z0.h] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid offset type. + +stnt1b { z0.d }, p0, [z0.d, z1.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: stnt1b { z0.d }, p0, [z0.d, z1.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// restricted predicate has range [0, 7]. + +stnt1b { z27.d }, p8, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: stnt1b { z27.d }, p8, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid vector list. + +stnt1b { }, p0, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected +// CHECK-NEXT: stnt1b { }, p0, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +stnt1b { z0.d, z1.d }, p0, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: stnt1b { z0.d, z1.d }, p0, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +stnt1b { v0.2d }, p0, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: stnt1b { v0.2d }, p0, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +stnt1b { z0.d }, p0, [z0.d, x0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: stnt1b { z0.d }, p0, [z0.d, x0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +stnt1b { z0.s }, p0, [z0.s, x0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: stnt1b { z0.s }, p0, [z0.s, x0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE2/stnt1b.s b/test/MC/AArch64/SVE2/stnt1b.s new file mode 100644 index 00000000000..cab8a6b7f30 --- /dev/null +++ b/test/MC/AArch64/SVE2/stnt1b.s @@ -0,0 +1,80 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +stnt1b z0.s, p0, [z1.s] +// CHECK-INST: stnt1b { z0.s }, p0, [z1.s] +// CHECK-ENCODING: [0x20,0x20,0x5f,0xe4] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 20 5f e4 + +stnt1b z31.s, p7, [z31.s, xzr] +// CHECK-INST: stnt1b { z31.s }, p7, [z31.s] +// CHECK-ENCODING: [0xff,0x3f,0x5f,0xe4] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 3f 5f e4 + +stnt1b z31.s, p7, [z31.s, x0] +// CHECK-INST: stnt1b { z31.s }, p7, [z31.s, x0] +// CHECK-ENCODING: [0xff,0x3f,0x40,0xe4] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 3f 40 e4 + +stnt1b z0.d, p0, [z1.d] +// CHECK-INST: stnt1b { z0.d }, p0, [z1.d] +// CHECK-ENCODING: [0x20,0x20,0x1f,0xe4] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 20 1f e4 + +stnt1b z31.d, p7, [z31.d, xzr] +// CHECK-INST: stnt1b { z31.d }, p7, [z31.d] +// CHECK-ENCODING: [0xff,0x3f,0x1f,0xe4] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 3f 1f e4 + +stnt1b z31.d, p7, [z31.d, x0] +// CHECK-INST: stnt1b { z31.d }, p7, [z31.d, x0] +// CHECK-ENCODING: [0xff,0x3f,0x00,0xe4] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 3f 00 e4 + +stnt1b { z0.s }, p0, [z1.s] +// CHECK-INST: stnt1b { z0.s }, p0, [z1.s] +// CHECK-ENCODING: [0x20,0x20,0x5f,0xe4] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 20 5f e4 + +stnt1b { z31.s }, p7, [z31.s, xzr] +// CHECK-INST: stnt1b { z31.s }, p7, [z31.s] +// CHECK-ENCODING: [0xff,0x3f,0x5f,0xe4] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 3f 5f e4 + +stnt1b { z31.s }, p7, [z31.s, x0] +// CHECK-INST: stnt1b { z31.s }, p7, [z31.s, x0] +// CHECK-ENCODING: [0xff,0x3f,0x40,0xe4] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 3f 40 e4 + +stnt1b { z0.d }, p0, [z1.d] +// CHECK-INST: stnt1b { z0.d }, p0, [z1.d] +// CHECK-ENCODING: [0x20,0x20,0x1f,0xe4] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 20 1f e4 + +stnt1b { z31.d }, p7, [z31.d, xzr] +// CHECK-INST: stnt1b { z31.d }, p7, [z31.d] +// CHECK-ENCODING: [0xff,0x3f,0x1f,0xe4] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 3f 1f e4 + +stnt1b { z31.d }, p7, [z31.d, x0] +// CHECK-INST: stnt1b { z31.d }, p7, [z31.d, x0] +// CHECK-ENCODING: [0xff,0x3f,0x00,0xe4] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 3f 00 e4 diff --git a/test/MC/AArch64/SVE2/stnt1d-diagnostics.s b/test/MC/AArch64/SVE2/stnt1d-diagnostics.s new file mode 100644 index 00000000000..c5be82611c5 --- /dev/null +++ b/test/MC/AArch64/SVE2/stnt1d-diagnostics.s @@ -0,0 +1,82 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// --------------------------------------------------------------------------// +// Invalid result type. + +stnt1d { z0.b }, p0, [z0.s] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: stnt1d { z0.b }, p0, [z0.s] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +stnt1d { z0.h }, p0, [z0.s] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: stnt1d { z0.h }, p0, [z0.s] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +stnt1d { z0.s }, p0, [z0.s] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: stnt1d { z0.s }, p0, [z0.s] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid base vector. + +stnt1d { z0.d }, p0, [z0.b] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: stnt1d { z0.d }, p0, [z0.b] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid offset type. + +stnt1d { z0.d }, p0, [z0.d, z1.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: stnt1d { z0.d }, p0, [z0.d, z1.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// restricted predicate has range [0, 7]. + +stnt1d { z27.d }, p8, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: stnt1d { z27.d }, p8, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid vector list. + +stnt1d { }, p0, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected +// CHECK-NEXT: stnt1d { }, p0, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +stnt1d { z0.d, z1.d }, p0, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: stnt1d { z0.d, z1.d }, p0, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +stnt1d { v0.2d }, p0, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: stnt1d { v0.2d }, p0, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +stnt1d { z0.d }, p0, [z0.d, x0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: stnt1d { z0.d }, p0, [z0.d, x0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +stnt1d { z0.d }, p0, [z0.d, x0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: stnt1d { z0.d }, p0, [z0.d, x0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE2/stnt1d.s b/test/MC/AArch64/SVE2/stnt1d.s new file mode 100644 index 00000000000..462b8bce010 --- /dev/null +++ b/test/MC/AArch64/SVE2/stnt1d.s @@ -0,0 +1,44 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +stnt1d z0.d, p0, [z1.d] +// CHECK-INST: stnt1d { z0.d }, p0, [z1.d] +// CHECK-ENCODING: [0x20,0x20,0x9f,0xe5] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 20 9f e5 + +stnt1d z31.d, p7, [z31.d, xzr] +// CHECK-INST: stnt1d { z31.d }, p7, [z31.d] +// CHECK-ENCODING: [0xff,0x3f,0x9f,0xe5] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 3f 9f e5 + +stnt1d z31.d, p7, [z31.d, x0] +// CHECK-INST: stnt1d { z31.d }, p7, [z31.d, x0] +// CHECK-ENCODING: [0xff,0x3f,0x80,0xe5] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 3f 80 e5 + +stnt1d { z0.d }, p0, [z1.d] +// CHECK-INST: stnt1d { z0.d }, p0, [z1.d] +// CHECK-ENCODING: [0x20,0x20,0x9f,0xe5] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 20 9f e5 + +stnt1d { z31.d }, p7, [z31.d, xzr] +// CHECK-INST: stnt1d { z31.d }, p7, [z31.d] +// CHECK-ENCODING: [0xff,0x3f,0x9f,0xe5] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 3f 9f e5 + +stnt1d { z31.d }, p7, [z31.d, x0] +// CHECK-INST: stnt1d { z31.d }, p7, [z31.d, x0] +// CHECK-ENCODING: [0xff,0x3f,0x80,0xe5] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 3f 80 e5 diff --git a/test/MC/AArch64/SVE2/stnt1h-diagnostics.s b/test/MC/AArch64/SVE2/stnt1h-diagnostics.s new file mode 100644 index 00000000000..db60d05b7c7 --- /dev/null +++ b/test/MC/AArch64/SVE2/stnt1h-diagnostics.s @@ -0,0 +1,82 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// --------------------------------------------------------------------------// +// Invalid result type. + +stnt1h { z0.b }, p0, [z0.s] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: stnt1h { z0.b }, p0, [z0.s] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +stnt1h { z0.h }, p0, [z0.s] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: stnt1h { z0.h }, p0, [z0.s] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid base vector. + +stnt1h { z0.s }, p0, [z0.b] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: stnt1h { z0.s }, p0, [z0.b] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +stnt1h { z0.d }, p0, [z0.h] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: stnt1h { z0.d }, p0, [z0.h] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid offset type. + +stnt1h { z0.d }, p0, [z0.d, z1.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: stnt1h { z0.d }, p0, [z0.d, z1.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// restricted predicate has range [0, 7]. + +stnt1h { z27.d }, p8, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: stnt1h { z27.d }, p8, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid vector list. + +stnt1h { }, p0, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected +// CHECK-NEXT: stnt1h { }, p0, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +stnt1h { z0.d, z1.d }, p0, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: stnt1h { z0.d, z1.d }, p0, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +stnt1h { v0.2d }, p0, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: stnt1h { v0.2d }, p0, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +stnt1h { z0.d }, p0, [z0.d, x0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: stnt1h { z0.d }, p0, [z0.d, x0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +stnt1h { z0.s }, p0, [z0.s, x0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: stnt1h { z0.s }, p0, [z0.s, x0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE2/stnt1h.s b/test/MC/AArch64/SVE2/stnt1h.s new file mode 100644 index 00000000000..07c9c328636 --- /dev/null +++ b/test/MC/AArch64/SVE2/stnt1h.s @@ -0,0 +1,80 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +stnt1h z0.s, p0, [z1.s] +// CHECK-INST: stnt1h { z0.s }, p0, [z1.s] +// CHECK-ENCODING: [0x20,0x20,0xdf,0xe4] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 20 df e4 + +stnt1h z31.s, p7, [z31.s, xzr] +// CHECK-INST: stnt1h { z31.s }, p7, [z31.s] +// CHECK-ENCODING: [0xff,0x3f,0xdf,0xe4] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 3f df e4 + +stnt1h z31.s, p7, [z31.s, x0] +// CHECK-INST: stnt1h { z31.s }, p7, [z31.s, x0] +// CHECK-ENCODING: [0xff,0x3f,0xc0,0xe4] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 3f c0 e4 + +stnt1h z0.d, p0, [z1.d] +// CHECK-INST: stnt1h { z0.d }, p0, [z1.d] +// CHECK-ENCODING: [0x20,0x20,0x9f,0xe4] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 20 9f e4 + +stnt1h z31.d, p7, [z31.d, xzr] +// CHECK-INST: stnt1h { z31.d }, p7, [z31.d] +// CHECK-ENCODING: [0xff,0x3f,0x9f,0xe4] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 3f 9f e4 + +stnt1h z31.d, p7, [z31.d, x0] +// CHECK-INST: stnt1h { z31.d }, p7, [z31.d, x0] +// CHECK-ENCODING: [0xff,0x3f,0x80,0xe4] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 3f 80 e4 + +stnt1h { z0.s }, p0, [z1.s] +// CHECK-INST: stnt1h { z0.s }, p0, [z1.s] +// CHECK-ENCODING: [0x20,0x20,0xdf,0xe4] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 20 df e4 + +stnt1h { z31.s }, p7, [z31.s, xzr] +// CHECK-INST: stnt1h { z31.s }, p7, [z31.s] +// CHECK-ENCODING: [0xff,0x3f,0xdf,0xe4] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 3f df e4 + +stnt1h { z31.s }, p7, [z31.s, x0] +// CHECK-INST: stnt1h { z31.s }, p7, [z31.s, x0] +// CHECK-ENCODING: [0xff,0x3f,0xc0,0xe4] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 3f c0 e4 + +stnt1h { z0.d }, p0, [z1.d] +// CHECK-INST: stnt1h { z0.d }, p0, [z1.d] +// CHECK-ENCODING: [0x20,0x20,0x9f,0xe4] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 20 9f e4 + +stnt1h { z31.d }, p7, [z31.d, xzr] +// CHECK-INST: stnt1h { z31.d }, p7, [z31.d] +// CHECK-ENCODING: [0xff,0x3f,0x9f,0xe4] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 3f 9f e4 + +stnt1h { z31.d }, p7, [z31.d, x0] +// CHECK-INST: stnt1h { z31.d }, p7, [z31.d, x0] +// CHECK-ENCODING: [0xff,0x3f,0x80,0xe4] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 3f 80 e4 diff --git a/test/MC/AArch64/SVE2/stnt1w-diagnostics.s b/test/MC/AArch64/SVE2/stnt1w-diagnostics.s new file mode 100644 index 00000000000..c552e36edce --- /dev/null +++ b/test/MC/AArch64/SVE2/stnt1w-diagnostics.s @@ -0,0 +1,82 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// --------------------------------------------------------------------------// +// Invalid result type. + +stnt1w { z0.b }, p0, [z0.s] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: stnt1w { z0.b }, p0, [z0.s] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +stnt1w { z0.h }, p0, [z0.s] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: stnt1w { z0.h }, p0, [z0.s] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid base vector. + +stnt1w { z0.s }, p0, [z0.b] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: stnt1w { z0.s }, p0, [z0.b] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +stnt1w { z0.d }, p0, [z0.h] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: stnt1w { z0.d }, p0, [z0.h] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid offset type. + +stnt1w { z0.d }, p0, [z0.d, z1.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: stnt1w { z0.d }, p0, [z0.d, z1.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// restricted predicate has range [0, 7]. + +stnt1w { z27.d }, p8, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: stnt1w { z27.d }, p8, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid vector list. + +stnt1w { }, p0, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected +// CHECK-NEXT: stnt1w { }, p0, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +stnt1w { z0.d, z1.d }, p0, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: stnt1w { z0.d, z1.d }, p0, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +stnt1w { v0.2d }, p0, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: stnt1w { v0.2d }, p0, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +stnt1w { z0.d }, p0, [z0.d, x0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: stnt1w { z0.d }, p0, [z0.d, x0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +stnt1w { z0.s }, p0, [z0.s, x0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: stnt1w { z0.s }, p0, [z0.s, x0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE2/stnt1w.s b/test/MC/AArch64/SVE2/stnt1w.s new file mode 100644 index 00000000000..90d4c8e6e14 --- /dev/null +++ b/test/MC/AArch64/SVE2/stnt1w.s @@ -0,0 +1,80 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +stnt1w z0.s, p0, [z1.s] +// CHECK-INST: stnt1w { z0.s }, p0, [z1.s] +// CHECK-ENCODING: [0x20,0x20,0x5f,0xe5] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 20 5f e5 + +stnt1w z31.s, p7, [z31.s, xzr] +// CHECK-INST: stnt1w { z31.s }, p7, [z31.s] +// CHECK-ENCODING: [0xff,0x3f,0x5f,0xe5] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 3f 5f e5 + +stnt1w z31.s, p7, [z31.s, x0] +// CHECK-INST: stnt1w { z31.s }, p7, [z31.s, x0] +// CHECK-ENCODING: [0xff,0x3f,0x40,0xe5] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 3f 40 e5 + +stnt1w z0.d, p0, [z1.d] +// CHECK-INST: stnt1w { z0.d }, p0, [z1.d] +// CHECK-ENCODING: [0x20,0x20,0x1f,0xe5] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 20 1f e5 + +stnt1w z31.d, p7, [z31.d, xzr] +// CHECK-INST: stnt1w { z31.d }, p7, [z31.d] +// CHECK-ENCODING: [0xff,0x3f,0x1f,0xe5] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 3f 1f e5 + +stnt1w z31.d, p7, [z31.d, x0] +// CHECK-INST: stnt1w { z31.d }, p7, [z31.d, x0] +// CHECK-ENCODING: [0xff,0x3f,0x00,0xe5] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 3f 00 e5 + +stnt1w { z0.s }, p0, [z1.s] +// CHECK-INST: stnt1w { z0.s }, p0, [z1.s] +// CHECK-ENCODING: [0x20,0x20,0x5f,0xe5] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 20 5f e5 + +stnt1w { z31.s }, p7, [z31.s, xzr] +// CHECK-INST: stnt1w { z31.s }, p7, [z31.s] +// CHECK-ENCODING: [0xff,0x3f,0x5f,0xe5] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 3f 5f e5 + +stnt1w { z31.s }, p7, [z31.s, x0] +// CHECK-INST: stnt1w { z31.s }, p7, [z31.s, x0] +// CHECK-ENCODING: [0xff,0x3f,0x40,0xe5] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 3f 40 e5 + +stnt1w { z0.d }, p0, [z1.d] +// CHECK-INST: stnt1w { z0.d }, p0, [z1.d] +// CHECK-ENCODING: [0x20,0x20,0x1f,0xe5] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 20 1f e5 + +stnt1w { z31.d }, p7, [z31.d, xzr] +// CHECK-INST: stnt1w { z31.d }, p7, [z31.d] +// CHECK-ENCODING: [0xff,0x3f,0x1f,0xe5] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 3f 1f e5 + +stnt1w { z31.d }, p7, [z31.d, x0] +// CHECK-INST: stnt1w { z31.d }, p7, [z31.d, x0] +// CHECK-ENCODING: [0xff,0x3f,0x00,0xe5] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 3f 00 e5 -- 2.40.0