From b098c5b8bbbfc29936ebf991b5162e7b8c1cd331 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Sun, 21 Apr 2019 05:18:04 +0000 Subject: [PATCH] [X86] Don't form masked vfpclass instruction from and+vfpclass unless the fpclass only has a single use. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@358841 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/X86/X86InstrAVX512.td | 64 ++++++++++++++++++-------------- 1 file changed, 36 insertions(+), 28 deletions(-) diff --git a/lib/Target/X86/X86InstrAVX512.td b/lib/Target/X86/X86InstrAVX512.td index 853f1f73a28..d3adc06441f 100644 --- a/lib/Target/X86/X86InstrAVX512.td +++ b/lib/Target/X86/X86InstrAVX512.td @@ -2596,16 +2596,27 @@ let Predicates = [HasAVX512] in { // ---------------------------------------------------------------- // FPClass + +def X86Vfpclasss_su : PatFrag<(ops node:$src1, node:$src2), + (X86Vfpclasss node:$src1, node:$src2), [{ + return N->hasOneUse(); +}]>; + +def X86Vfpclass_su : PatFrag<(ops node:$src1, node:$src2), + (X86Vfpclass node:$src1, node:$src2), [{ + return N->hasOneUse(); +}]>; + //handle fpclass instruction mask = op(reg_scalar,imm) // op(mem_scalar,imm) -multiclass avx512_scalar_fpclass opc, string OpcodeStr, SDNode OpNode, +multiclass avx512_scalar_fpclass opc, string OpcodeStr, X86FoldableSchedWrite sched, X86VectorVTInfo _, Predicate prd> { let Predicates = [prd], ExeDomain = _.ExeDomain in { def rr : AVX512, Sched<[sched]>; def rrk : AVX512 opc, string OpcodeStr, SDNode OpNode, OpcodeStr##_.Suffix# "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}", [(set _.KRC:$dst,(and _.KRCWM:$mask, - (OpNode (_.VT _.RC:$src1), + (X86Vfpclasss_su (_.VT _.RC:$src1), (i32 imm:$src2))))]>, EVEX_K, Sched<[sched]>; def rm : AVX512 opc, string OpcodeStr, SDNode OpNode, OpcodeStr##_.Suffix## "\t{$src2, $src1, $dst|$dst, $src1, $src2}", [(set _.KRC:$dst, - (OpNode _.ScalarIntMemCPat:$src1, - (i32 imm:$src2)))]>, + (X86Vfpclasss _.ScalarIntMemCPat:$src1, + (i32 imm:$src2)))]>, Sched<[sched.Folded, sched.ReadAfterFold]>; def rmk : AVX512, EVEX_K, Sched<[sched.Folded, sched.ReadAfterFold]>; } @@ -2638,14 +2649,14 @@ multiclass avx512_scalar_fpclass opc, string OpcodeStr, SDNode OpNode, //handle fpclass instruction mask = fpclass(reg_vec, reg_vec, imm) // fpclass(reg_vec, mem_vec, imm) // fpclass(reg_vec, broadcast(eltVt), imm) -multiclass avx512_vector_fpclass opc, string OpcodeStr, SDNode OpNode, +multiclass avx512_vector_fpclass opc, string OpcodeStr, X86FoldableSchedWrite sched, X86VectorVTInfo _, string mem, string broadcast>{ let ExeDomain = _.ExeDomain in { def rr : AVX512, Sched<[sched]>; def rrk : AVX512 opc, string OpcodeStr, SDNode OpNode, OpcodeStr##_.Suffix# "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}", [(set _.KRC:$dst,(and _.KRCWM:$mask, - (OpNode (_.VT _.RC:$src1), + (X86Vfpclass_su (_.VT _.RC:$src1), (i32 imm:$src2))))]>, EVEX_K, Sched<[sched]>; def rm : AVX512, Sched<[sched.Folded, sched.ReadAfterFold]>; @@ -2668,7 +2679,7 @@ multiclass avx512_vector_fpclass opc, string OpcodeStr, SDNode OpNode, (ins _.KRCWM:$mask, _.MemOp:$src1, i32u8imm:$src2), OpcodeStr##_.Suffix##mem# "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}", - [(set _.KRC:$dst, (and _.KRCWM:$mask, (OpNode + [(set _.KRC:$dst, (and _.KRCWM:$mask, (X86Vfpclass_su (_.VT (_.LdFrag addr:$src1)), (i32 imm:$src2))))]>, EVEX_K, Sched<[sched.Folded, sched.ReadAfterFold]>; @@ -2677,7 +2688,7 @@ multiclass avx512_vector_fpclass opc, string OpcodeStr, SDNode OpNode, OpcodeStr##_.Suffix##broadcast##"\t{$src2, ${src1}"## _.BroadcastStr##", $dst|$dst, ${src1}" ##_.BroadcastStr##", $src2}", - [(set _.KRC:$dst,(OpNode + [(set _.KRC:$dst,(X86Vfpclass (_.VT (X86VBroadcast (_.ScalarLdFrag addr:$src1))), (i32 imm:$src2)))]>, @@ -2687,7 +2698,7 @@ multiclass avx512_vector_fpclass opc, string OpcodeStr, SDNode OpNode, OpcodeStr##_.Suffix##broadcast##"\t{$src2, ${src1}"## _.BroadcastStr##", $dst {${mask}}|$dst {${mask}}, ${src1}"## _.BroadcastStr##", $src2}", - [(set _.KRC:$dst,(and _.KRCWM:$mask, (OpNode + [(set _.KRC:$dst,(and _.KRCWM:$mask, (X86Vfpclass_su (_.VT (X86VBroadcast (_.ScalarLdFrag addr:$src1))), (i32 imm:$src2))))]>, @@ -2696,42 +2707,39 @@ multiclass avx512_vector_fpclass opc, string OpcodeStr, SDNode OpNode, } multiclass avx512_vector_fpclass_all opc, SDNode OpNode, - X86SchedWriteWidths sched, Predicate prd, - string broadcast>{ + bits<8> opc, X86SchedWriteWidths sched, + Predicate prd, string broadcast>{ let Predicates = [prd] in { - defm Z : avx512_vector_fpclass, EVEX_V512; } let Predicates = [prd, HasVLX] in { - defm Z128 : avx512_vector_fpclass, EVEX_V128; - defm Z256 : avx512_vector_fpclass, EVEX_V256; } } multiclass avx512_fp_fpclass_all opcVec, - bits<8> opcScalar, SDNode VecOpNode, - SDNode ScalarOpNode, X86SchedWriteWidths sched, + bits<8> opcScalar, X86SchedWriteWidths sched, Predicate prd> { defm PS : avx512_vector_fpclass_all, + sched, prd, "{l}">, EVEX_CD8<32, CD8VF>; defm PD : avx512_vector_fpclass_all, + sched, prd, "{q}">, EVEX_CD8<64, CD8VF> , VEX_W; - defm SSZ : avx512_scalar_fpclass, VEX_LIG, EVEX_CD8<32, CD8VT1>; - defm SDZ : avx512_scalar_fpclass, VEX_LIG, EVEX_CD8<64, CD8VT1>, VEX_W; } -defm VFPCLASS : avx512_fp_fpclass_all<"vfpclass", 0x66, 0x67, X86Vfpclass, - X86Vfpclasss, SchedWriteFCmp, HasDQI>, - AVX512AIi8Base, EVEX; +defm VFPCLASS : avx512_fp_fpclass_all<"vfpclass", 0x66, 0x67, SchedWriteFCmp, + HasDQI>, AVX512AIi8Base, EVEX; //----------------------------------------------------------------- // Mask register copy, including -- 2.50.1