From af2984265a8ea2fa35416e8e2f403b4513541520 Mon Sep 17 00:00:00 2001 From: Krzysztof Parzyszek Date: Fri, 14 Dec 2018 22:33:48 +0000 Subject: [PATCH] [Hexagon] Add patterns for shifts of v2i16 This fixes https://llvm.org/PR39983. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@349202 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Hexagon/HexagonPatterns.td | 12 ++++++++++++ test/CodeGen/Hexagon/isel-vlsr-v2i16.ll | 16 ++++++++++++++++ 2 files changed, 28 insertions(+) create mode 100644 test/CodeGen/Hexagon/isel-vlsr-v2i16.ll diff --git a/lib/Target/Hexagon/HexagonPatterns.td b/lib/Target/Hexagon/HexagonPatterns.td index 0a7f578a60f..311b5a702d5 100644 --- a/lib/Target/Hexagon/HexagonPatterns.td +++ b/lib/Target/Hexagon/HexagonPatterns.td @@ -1170,6 +1170,18 @@ def: Pat<(srl V4I16:$b, (v4i16 (HexagonVSPLAT u4_0ImmPred:$c))), def: Pat<(shl V4I16:$b, (v4i16 (HexagonVSPLAT u4_0ImmPred:$c))), (S2_asl_i_vh V4I16:$b, imm:$c)>; +def: Pat<(HexagonVASR V2I16:$Rs, u4_0ImmPred:$S), + (LoReg (S2_asr_i_vh (ToAext64 $Rs), imm:$S))>; +def: Pat<(HexagonVASL V2I16:$Rs, u4_0ImmPred:$S), + (LoReg (S2_asl_i_vh (ToAext64 $Rs), imm:$S))>; +def: Pat<(HexagonVLSR V2I16:$Rs, u4_0ImmPred:$S), + (LoReg (S2_lsr_i_vh (ToAext64 $Rs), imm:$S))>; +def: Pat<(HexagonVASR V2I16:$Rs, I32:$Rt), + (LoReg (S2_asr_i_vh (ToAext64 $Rs), I32:$Rt))>; +def: Pat<(HexagonVASL V2I16:$Rs, I32:$Rt), + (LoReg (S2_asl_i_vh (ToAext64 $Rs), I32:$Rt))>; +def: Pat<(HexagonVLSR V2I16:$Rs, I32:$Rt), + (LoReg (S2_lsr_i_vh (ToAext64 $Rs), I32:$Rt))>; // --(9) Arithmetic/bitwise ---------------------------------------------- // diff --git a/test/CodeGen/Hexagon/isel-vlsr-v2i16.ll b/test/CodeGen/Hexagon/isel-vlsr-v2i16.ll new file mode 100644 index 00000000000..995ce06129d --- /dev/null +++ b/test/CodeGen/Hexagon/isel-vlsr-v2i16.ll @@ -0,0 +1,16 @@ +; RUN: llc -march=hexagon < %s | FileCheck %s + +; This used to crash with "cannot select" error. +; CHECK: vlsrh(r1:0,#4) + +target triple = "hexagon-unknown-linux-gnu" + +define <2 x i16> @foo(<2 x i32>* nocapture %v) nounwind { + %vec = load <2 x i32>, <2 x i32>* %v, align 8 + %trunc = trunc <2 x i32> %vec to <2 x i16> + %r = lshr <2 x i16> %trunc, + ret <2 x i16> %r +} + +attributes #0 = { nounwind "target-cpu"="hexagonv60" } + -- 2.50.1