From af1205bfaedb25a72f6709a3564b721f3deb8036 Mon Sep 17 00:00:00 2001 From: Nirav Dave Date: Wed, 5 Apr 2017 15:42:48 +0000 Subject: [PATCH] [SystemZ] Prevent Merging Bitcast with non-normal loads Fixes PR32505. Reviewers: uweigand, jonpa Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D31609 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299552 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/SystemZ/SystemZISelLowering.cpp | 5 +++-- test/CodeGen/SystemZ/pr32505.ll | 20 ++++++++++++++++++++ 2 files changed, 23 insertions(+), 2 deletions(-) create mode 100644 test/CodeGen/SystemZ/pr32505.ll diff --git a/lib/Target/SystemZ/SystemZISelLowering.cpp b/lib/Target/SystemZ/SystemZISelLowering.cpp index 5078accbaf3..2db35eabe63 100644 --- a/lib/Target/SystemZ/SystemZISelLowering.cpp +++ b/lib/Target/SystemZ/SystemZISelLowering.cpp @@ -2792,8 +2792,9 @@ SDValue SystemZTargetLowering::lowerBITCAST(SDValue Op, // but we need this case for bitcasts that are created during lowering // and which are then lowered themselves. if (auto *LoadN = dyn_cast(In)) - return DAG.getLoad(ResVT, DL, LoadN->getChain(), LoadN->getBasePtr(), - LoadN->getMemOperand()); + if (ISD::isNormalLoad(LoadN)) + return DAG.getLoad(ResVT, DL, LoadN->getChain(), LoadN->getBasePtr(), + LoadN->getMemOperand()); if (InVT == MVT::i32 && ResVT == MVT::f32) { SDValue In64; diff --git a/test/CodeGen/SystemZ/pr32505.ll b/test/CodeGen/SystemZ/pr32505.ll new file mode 100644 index 00000000000..6abad022016 --- /dev/null +++ b/test/CodeGen/SystemZ/pr32505.ll @@ -0,0 +1,20 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mcpu=zEC12 -o - %s | FileCheck %s + +target triple = "s390x-ibm-linux" + +define <2 x float> @pr32505(<2 x i8> * %a) { +; CHECK-LABEL: pr32505: +; CHECK: # BB#0: +; CHECK-NEXT: lbh %r0, 0(%r2) +; CHECK-NEXT: ldgr %f0, %r0 +; CHECK-NEXT: lbh %r0, 1(%r2) +; CHECK-NEXT: ldgr %f2, %r0 +; CHECK-NEXT: # kill: %F0S %F0S %F0D +; CHECK-NEXT: # kill: %F2S %F2S %F2D +; CHECK-NEXT: br %r14 + %L17 = load <2 x i8>, <2 x i8>* %a + %Se21 = sext <2 x i8> %L17 to <2 x i32> + %BC = bitcast <2 x i32> %Se21 to <2 x float> + ret <2 x float> %BC +} -- 2.50.1