From ad68aabcad5544ed0a6654674246b4a9f65a0c6e Mon Sep 17 00:00:00 2001 From: Simon Dardis Date: Tue, 11 Jul 2017 18:03:20 +0000 Subject: [PATCH] [mips][mt][1/7] Add the MT ASE as a subtarget feature. Preparatory work for adding the MIPS MT (multi-threading) ASE instructions. Reviewers: slthakur, atanasyan Differential Revision: https://reviews.llvm.org/D35247 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307679 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/AsmParser/MipsAsmParser.cpp | 3 +++ lib/Target/Mips/MCTargetDesc/MipsABIFlagsSection.h | 2 ++ lib/Target/Mips/Mips.td | 2 ++ lib/Target/Mips/MipsSubtarget.cpp | 3 ++- lib/Target/Mips/MipsSubtarget.h | 4 ++++ test/MC/Mips/mt/abiflag.s | 10 ++++++++++ 6 files changed, 23 insertions(+), 1 deletion(-) create mode 100644 test/MC/Mips/mt/abiflag.s diff --git a/lib/Target/Mips/AsmParser/MipsAsmParser.cpp b/lib/Target/Mips/AsmParser/MipsAsmParser.cpp index f978f8cc7fd..4a1d585bbbc 100644 --- a/lib/Target/Mips/AsmParser/MipsAsmParser.cpp +++ b/lib/Target/Mips/AsmParser/MipsAsmParser.cpp @@ -628,6 +628,9 @@ public: bool useSoftFloat() const { return getSTI().getFeatureBits()[Mips::FeatureSoftFloat]; } + bool hasMT() const { + return getSTI().getFeatureBits()[Mips::FeatureMT]; + } /// Warn if RegIndex is the same as the current AT. void warnIfRegIndexIsAT(unsigned RegIndex, SMLoc Loc); diff --git a/lib/Target/Mips/MCTargetDesc/MipsABIFlagsSection.h b/lib/Target/Mips/MCTargetDesc/MipsABIFlagsSection.h index f3854102702..9abd4f1d6b0 100644 --- a/lib/Target/Mips/MCTargetDesc/MipsABIFlagsSection.h +++ b/lib/Target/Mips/MCTargetDesc/MipsABIFlagsSection.h @@ -159,6 +159,8 @@ public: ASESet |= Mips::AFL_ASE_MICROMIPS; if (P.inMips16Mode()) ASESet |= Mips::AFL_ASE_MIPS16; + if (P.hasMT()) + ASESet |= Mips::AFL_ASE_MT; } template diff --git a/lib/Target/Mips/Mips.td b/lib/Target/Mips/Mips.td index f24761d7d10..d2f0fdcc6cc 100644 --- a/lib/Target/Mips/Mips.td +++ b/lib/Target/Mips/Mips.td @@ -188,6 +188,8 @@ def FeatureUseTCCInDIV : SubtargetFeature< def FeatureMadd4 : SubtargetFeature<"nomadd4", "DisableMadd4", "true", "Disable 4-operand madd.fmt and related instructions">; +def FeatureMT : SubtargetFeature<"mt", "HasMT", "true", "Mips MT ASE">; + //===----------------------------------------------------------------------===// // Mips processors supported. //===----------------------------------------------------------------------===// diff --git a/lib/Target/Mips/MipsSubtarget.cpp b/lib/Target/Mips/MipsSubtarget.cpp index 154d5825427..eba21e0a1c6 100644 --- a/lib/Target/Mips/MipsSubtarget.cpp +++ b/lib/Target/Mips/MipsSubtarget.cpp @@ -70,7 +70,8 @@ MipsSubtarget::MipsSubtarget(const Triple &TT, StringRef CPU, StringRef FS, InMips16HardFloat(Mips16HardFloat), InMicroMipsMode(false), HasDSP(false), HasDSPR2(false), HasDSPR3(false), AllowMixed16_32(Mixed16_32 | Mips_Os16), Os16(Mips_Os16), HasMSA(false), UseTCCInDIV(false), HasSym32(false), - HasEVA(false), DisableMadd4(false), TM(TM), TargetTriple(TT), TSInfo(), + HasEVA(false), DisableMadd4(false), HasMT(false), TM(TM), + TargetTriple(TT), TSInfo(), InstrInfo( MipsInstrInfo::create(initializeSubtargetDependencies(CPU, FS, TM))), FrameLowering(MipsFrameLowering::create(*this)), diff --git a/lib/Target/Mips/MipsSubtarget.h b/lib/Target/Mips/MipsSubtarget.h index ccd47f00c0d..7619e7b0861 100644 --- a/lib/Target/Mips/MipsSubtarget.h +++ b/lib/Target/Mips/MipsSubtarget.h @@ -149,6 +149,9 @@ class MipsSubtarget : public MipsGenSubtargetInfo { // related instructions. bool DisableMadd4; + // HasMT -- support MT ASE. + bool HasMT; + InstrItineraryData InstrItins; // We can override the determination of whether we are in mips16 mode @@ -259,6 +262,7 @@ public: bool hasMSA() const { return HasMSA; } bool disableMadd4() const { return DisableMadd4; } bool hasEVA() const { return HasEVA; } + bool hasMT() const { return HasMT; } bool useSmallSection() const { return UseSmallSection; } bool hasStandardEncoding() const { return !inMips16Mode(); } diff --git a/test/MC/Mips/mt/abiflag.s b/test/MC/Mips/mt/abiflag.s new file mode 100644 index 00000000000..b4769cba4c2 --- /dev/null +++ b/test/MC/Mips/mt/abiflag.s @@ -0,0 +1,10 @@ +# RUN: llvm-mc < %s -arch=mips -mcpu=mips32r2 -mattr=+mt -filetype=obj -o - \ +# RUN: | llvm-readobj -mips-abi-flags | FileCheck %s + +# Test that the usage of the MT ASE is recorded in .MIPS.abiflags + +# CHECK: ASEs +# CHECK-NEXT: MT (0x40) + + .text + nop -- 2.49.0