From ab5ea555b20cb17edc2bb2a185919560b9d8a36e Mon Sep 17 00:00:00 2001 From: Joerg Sonnenberger Date: Wed, 2 Nov 2016 15:00:31 +0000 Subject: [PATCH] Create the virtual register for the global base in the intersection of GPRC and GPRC_NOR0 (or the 64bit equivalent) and not just the latter. GPRC_NOR0 contains ZERO as alternative meaning of r0 and is therefore not a true subclass of GPRC. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285813 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/PowerPC/PPCISelDAGToDAG.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp index cf8b858c6a7..1e51c1f651c 100644 --- a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp +++ b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp @@ -334,12 +334,12 @@ SDNode *PPCDAGToDAGISel::getGlobalBaseReg() { } } else { GlobalBaseReg = - RegInfo->createVirtualRegister(&PPC::GPRC_NOR0RegClass); + RegInfo->createVirtualRegister(&PPC::GPRC_and_GPRC_NOR0RegClass); BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR)); BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR), GlobalBaseReg); } } else { - GlobalBaseReg = RegInfo->createVirtualRegister(&PPC::G8RC_NOX0RegClass); + GlobalBaseReg = RegInfo->createVirtualRegister(&PPC::G8RC_and_G8RC_NOX0RegClass); BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR8)); BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR8), GlobalBaseReg); } -- 2.49.0