From aa39cd364debbeae33c108fd2b12926d33122c2c Mon Sep 17 00:00:00 2001
From: Diana Picus <diana.picus@linaro.org>
Date: Fri, 7 Apr 2017 10:50:02 +0000
Subject: [PATCH] [ARM] GlobalISel: Support frem for 64-bit values

Legalize to a libcall.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299756 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/ARM/ARMLegalizerInfo.cpp           |  1 +
 test/CodeGen/ARM/GlobalISel/arm-isel-fp.ll    |  6 +++
 .../ARM/GlobalISel/arm-legalize-fp.mir        | 52 +++++++++++++++++++
 3 files changed, 59 insertions(+)

diff --git a/lib/Target/ARM/ARMLegalizerInfo.cpp b/lib/Target/ARM/ARMLegalizerInfo.cpp
index 64cca82f13e..ccafba968ca 100644
--- a/lib/Target/ARM/ARMLegalizerInfo.cpp
+++ b/lib/Target/ARM/ARMLegalizerInfo.cpp
@@ -66,6 +66,7 @@ ARMLegalizerInfo::ARMLegalizerInfo(const ARMSubtarget &ST) {
   }
 
   setAction({G_FREM, s32}, Libcall);
+  setAction({G_FREM, s64}, Libcall);
 
   computeTables();
 }
diff --git a/test/CodeGen/ARM/GlobalISel/arm-isel-fp.ll b/test/CodeGen/ARM/GlobalISel/arm-isel-fp.ll
index a1b35fd231a..7c653556514 100644
--- a/test/CodeGen/ARM/GlobalISel/arm-isel-fp.ll
+++ b/test/CodeGen/ARM/GlobalISel/arm-isel-fp.ll
@@ -9,3 +9,9 @@ define arm_aapcscc float @test_frem_float(float %x, float %y) {
   ret float %r
 }
 
+define arm_aapcscc double @test_frem_double(double %x, double %y) {
+; CHECK-LABEL: test_frem_double:
+; CHECK: blx fmod
+  %r = frem double %x, %y
+  ret double %r
+}
diff --git a/test/CodeGen/ARM/GlobalISel/arm-legalize-fp.mir b/test/CodeGen/ARM/GlobalISel/arm-legalize-fp.mir
index 01a2ee562f5..a80f9a6d411 100644
--- a/test/CodeGen/ARM/GlobalISel/arm-legalize-fp.mir
+++ b/test/CodeGen/ARM/GlobalISel/arm-legalize-fp.mir
@@ -3,6 +3,7 @@
 # RUN: llc -mtriple arm-- -float-abi=soft -global-isel -run-pass=legalizer %s -o - | FileCheck %s
 --- |
   define void @test_frem_float() { ret void }
+  define void @test_frem_double() { ret void }
 ...
 ---
 name:            test_frem_float
@@ -35,3 +36,54 @@ body:             |
     %r0 = COPY %2(s32)
     BX_RET 14, _, implicit %r0
 ...
+---
+name:            test_frem_double
+# CHECK-LABEL: name: test_frem_double
+legalized:       false
+# CHECK: legalized: true
+regBankSelected: false
+selected:        false
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+  - { id: 3, class: _ }
+  - { id: 4, class: _ }
+  - { id: 5, class: _ }
+  - { id: 6, class: _ }
+  - { id: 7, class: _ }
+  - { id: 8, class: _ }
+body:             |
+  bb.0:
+    liveins: %r0, %r1, %r2, %r3
+
+    ; The inputs may be in the wrong order (depending on the target's
+    ; endianness), but that's orthogonal to what we're trying to test here. We
+    ; only need to check that the first value, received through R0-R1, ends up
+    ; in R0-R1 or R1-R0, and the second value, received through R2-R3, ends up
+    ; in R2-R3 or R3-R2, when passed to fmod.
+    ; CHECK-DAG: [[X0:%[0-9]+]](s32) = COPY %r0
+    ; CHECK-DAG: [[X1:%[0-9]+]](s32) = COPY %r1
+    ; CHECK-DAG: [[Y0:%[0-9]+]](s32) = COPY %r2
+    ; CHECK-DAG: [[Y1:%[0-9]+]](s32) = COPY %r3
+    %0(s32) = COPY %r0
+    %1(s32) = COPY %r1
+    %2(s32) = COPY %r2
+    %3(s32) = COPY %r3
+    %4(s64) = G_SEQUENCE %0(s32), 0, %1(s32), 32
+    %5(s64) = G_SEQUENCE %2(s32), 0, %3(s32), 32
+    ; CHECK: ADJCALLSTACKDOWN
+    ; CHECK-DAG: %r{{[0-1]}} = COPY [[X0]]
+    ; CHECK-DAG: %r{{[0-1]}} = COPY [[X1]]
+    ; CHECK-DAG: %r{{[2-3]}} = COPY [[Y0]]
+    ; CHECK-DAG: %r{{[2-3]}} = COPY [[Y1]]
+    ; CHECK: BLX $fmod, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0, implicit-def %r1
+    ; CHECK: ADJCALLSTACKUP
+    %6(s64) = G_FREM %4, %5
+    %7(s32) = G_EXTRACT %6(s64), 0
+    %8(s32) = G_EXTRACT %6(s64), 32
+    %r0 = COPY %7(s32)
+    %r1 = COPY %8(s32)
+    BX_RET 14, _, implicit %r0, implicit %r1
+...
-- 
2.40.0