From aa09aeb5c0e40fdc72538cc3a79620816ad38f3e Mon Sep 17 00:00:00 2001 From: David Majnemer Date: Sun, 8 May 2016 08:15:50 +0000 Subject: [PATCH] [X86] Promote several single precision FP libcalls on Windows A number of libcalls don't exist in any particular lib but are, instead, defined in math.h as inline functions (even in C mode!). Don't rely on their existence when lowering @llvm.{cos,sin,floor,..}.f32, promote them instead. N.B. We had logic to handle FREM but were missing out on a number of others. This change generalizes the FREM handling. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268875 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Analysis/TargetLibraryInfo.cpp | 2 ++ lib/Target/X86/X86ISelLowering.cpp | 22 ++++++++++++---------- 2 files changed, 14 insertions(+), 10 deletions(-) diff --git a/lib/Analysis/TargetLibraryInfo.cpp b/lib/Analysis/TargetLibraryInfo.cpp index 36f83adeaa1..71f15b155cb 100644 --- a/lib/Analysis/TargetLibraryInfo.cpp +++ b/lib/Analysis/TargetLibraryInfo.cpp @@ -205,6 +205,8 @@ static void initialize(TargetLibraryInfoImpl &TLI, const Triple &T, TLI.setUnavailable(LibFunc::fmaxf); TLI.setUnavailable(LibFunc::fmodf); TLI.setUnavailable(LibFunc::logf); + TLI.setUnavailable(LibFunc::log10f); + TLI.setUnavailable(LibFunc::modff); TLI.setUnavailable(LibFunc::powf); TLI.setUnavailable(LibFunc::sinf); TLI.setUnavailable(LibFunc::sinhf); diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index fbf06da75dd..939edf6345c 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -308,16 +308,7 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM, setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand); - if (Subtarget.is32Bit() && Subtarget.isTargetKnownWindowsMSVC()) { - // On 32 bit MSVC, `fmodf(f32)` is not defined - only `fmod(f64)` - // is. We should promote the value to 64-bits to solve this. - // This is what the CRT headers do - `fmodf` is an inline header - // function casting to f64 and calling `fmod`. - setOperationAction(ISD::FREM , MVT::f32 , Promote); - } else { - setOperationAction(ISD::FREM , MVT::f32 , Expand); - } - + setOperationAction(ISD::FREM , MVT::f32 , Expand); setOperationAction(ISD::FREM , MVT::f64 , Expand); setOperationAction(ISD::FREM , MVT::f80 , Expand); setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom); @@ -1585,6 +1576,17 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM, setOperationAction(ISD::UDIVREM, MVT::i128, Custom); } + // On 32 bit MSVC, `fmodf(f32)` is not defined - only `fmod(f64)` + // is. We should promote the value to 64-bits to solve this. + // This is what the CRT headers do - `fmodf` is an inline header + // function casting to f64 and calling `fmod`. + if (Subtarget.is32Bit() && Subtarget.isTargetKnownWindowsMSVC()) + for (ISD::NodeType Op : + {ISD::FCEIL, ISD::FCOS, ISD::FEXP, ISD::FFLOOR, ISD::FREM, ISD::FLOG, + ISD::FLOG10, ISD::FPOW, ISD::FSIN}) + if (isOperationExpand(Op, MVT::f32)) + setOperationAction(Op, MVT::f32, Promote); + // We have target-specific dag combine patterns for the following nodes: setTargetDAGCombine(ISD::VECTOR_SHUFFLE); setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT); -- 2.50.1