From a9c167e82e03f97500735fb8fefedc57018f65f0 Mon Sep 17 00:00:00 2001 From: Krzysztof Parzyszek Date: Thu, 22 Sep 2016 20:59:41 +0000 Subject: [PATCH] [Hexagon] Remove USR_OVF from CtrRegs register class USR_OVF is a subregister of USR, which is a member of CtrRegs. Having both a register and its proper subregister in the same register class has bad consequences for lane mask calculation: based solely on the lane mask info, USR_OVF would not appear to be a subregister of USR. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@282192 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Hexagon/HexagonRegisterInfo.td | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/lib/Target/Hexagon/HexagonRegisterInfo.td b/lib/Target/Hexagon/HexagonRegisterInfo.td index 7f20aacc02f..c88c033dd4f 100644 --- a/lib/Target/Hexagon/HexagonRegisterInfo.td +++ b/lib/Target/Hexagon/HexagonRegisterInfo.td @@ -260,7 +260,10 @@ def CtrRegs : RegisterClass<"Hexagon", [i32], 32, (add LC0, SA0, LC1, SA1, P3_0, C5, M0, M1, C6, C7, C8, CS0, CS1, UPCL, UPCH, - USR, USR_OVF, UGP, GP, PC)>; + USR, UGP, GP, PC)>; + +let isAllocatable = 0 in +def UsrBits : RegisterClass<"Hexagon", [i1], 0, (add USR_OVF)>; let Size = 64, isAllocatable = 0 in def CtrRegs64 : RegisterClass<"Hexagon", [i64], 64, -- 2.50.1