From a53106e8e7908a62d7fde166e4d61495a5d05c3f Mon Sep 17 00:00:00 2001 From: John Brawn Date: Wed, 8 Mar 2017 12:49:18 +0000 Subject: [PATCH] [ARM] Split up lsl-zero test into two tests On Windows stderr and stdout happen to get interleaved in a way that causes the test to fail, so split it up into a test that checks for errors and a test that doesn't. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297273 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/MC/ARM/lsl-zero-errors.s | 103 ++++++++++++++++++++++++++++++++++ test/MC/ARM/lsl-zero.s | 101 +-------------------------------- 2 files changed, 105 insertions(+), 99 deletions(-) create mode 100644 test/MC/ARM/lsl-zero-errors.s diff --git a/test/MC/ARM/lsl-zero-errors.s b/test/MC/ARM/lsl-zero-errors.s new file mode 100644 index 00000000000..845507c069a --- /dev/null +++ b/test/MC/ARM/lsl-zero-errors.s @@ -0,0 +1,103 @@ +// RUN: not llvm-mc -triple=thumbv7 -show-encoding < %s 2>&1 | FileCheck --check-prefix=CHECK --check-prefix=CHECK-NONARM --check-prefix=CHECK-THUMBV7 %s +// RUN: not llvm-mc -triple=thumbv8 -show-encoding < %s 2>&1 | FileCheck --check-prefix=CHECK --check-prefix=CHECK-NONARM --check-prefix=CHECK-THUMBV8 %s +// RUN: llvm-mc -triple=armv7 -show-encoding < %s 2>&1 | FileCheck --check-prefix=CHECK --check-prefix=CHECK-ARM %s + + // lsl #0 is actually mov, so here we check that it behaves the same as + // mov with regards to the permitted registers + + // Using PC is invalid in thumb + lsl pc, r0, #0 + lsl r0, pc, #0 + lsl pc, pc, #0 + lsls pc, r0, #0 + lsls r0, pc, #0 + lsls pc, pc, #0 + +// CHECK-NONARM: error: instruction requires: arm-mode +// CHECK-NONARM-NEXT: lsl pc, r0, #0 +// CHECK-NONARM: error: instruction requires: arm-mode +// CHECK-NONARM-NEXT: lsl r0, pc, #0 +// CHECK-NONARM: error: instruction requires: arm-mode +// CHECK-NONARM-NEXT: lsl pc, pc, #0 +// CHECK-NONARM: error: instruction requires: arm-mode +// CHECK-NONARM-NEXT: lsls pc, r0, #0 +// CHECK-NONARM: error: instruction requires: arm-mode +// CHECK-NONARM-NEXT: lsls r0, pc, #0 +// CHECK-NONARM: error: instruction requires: arm-mode +// CHECK-NONARM-NEXT: lsls pc, pc, #0 + +// CHECK-ARM: mov pc, r0 @ encoding: [0x00,0xf0,0xa0,0xe1] +// CHECK-ARM: mov r0, pc @ encoding: [0x0f,0x00,0xa0,0xe1] +// CHECK-ARM: mov pc, pc @ encoding: [0x0f,0xf0,0xa0,0xe1] +// CHECK-ARM: movs pc, r0 @ encoding: [0x00,0xf0,0xb0,0xe1] +// CHECK-ARM: movs r0, pc @ encoding: [0x0f,0x00,0xb0,0xe1] +// CHECK-ARM: movs pc, pc @ encoding: [0x0f,0xf0,0xb0,0xe1] + + mov pc, r0, lsl #0 + mov r0, pc, lsl #0 + mov pc, pc, lsl #0 + movs pc, r0, lsl #0 + movs r0, pc, lsl #0 + movs pc, pc, lsl #0 + +// FIXME: Really the error we should be giving is "requires: arm-mode" +// CHECK-NONARM: error: invalid operand for instruction +// CHECK-NONARM-NEXT: mov pc, r0, lsl #0 +// CHECK-NONARM: error: invalid operand for instruction +// CHECK-NONARM-NEXT: mov r0, pc, lsl #0 +// CHECK-NONARM: error: invalid operand for instruction +// CHECK-NONARM-NEXT: mov pc, pc, lsl #0 +// CHECK-NONARM: error: invalid operand for instruction +// CHECK-NONARM-NEXT: movs pc, r0, lsl #0 +// CHECK-NONARM: error: invalid operand for instruction +// CHECK-NONARM-NEXT: movs r0, pc, lsl #0 +// CHECK-NONARM: error: invalid operand for instruction +// CHECK-NONARM-NEXT: movs pc, pc, lsl #0 + +// CHECK-ARM: mov pc, r0 @ encoding: [0x00,0xf0,0xa0,0xe1] +// CHECK-ARM: mov r0, pc @ encoding: [0x0f,0x00,0xa0,0xe1] +// CHECK-ARM: mov pc, pc @ encoding: [0x0f,0xf0,0xa0,0xe1] +// CHECK-ARM: movs pc, r0 @ encoding: [0x00,0xf0,0xb0,0xe1] +// CHECK-ARM: movs r0, pc @ encoding: [0x0f,0x00,0xb0,0xe1] +// CHECK-ARM: movs pc, pc @ encoding: [0x0f,0xf0,0xb0,0xe1] + + // Using SP is invalid before ARMv8 in thumb unless non-flags-setting + // and one of the source and destination is not SP + lsl sp, sp, #0 + lsls sp, sp, #0 + lsls r0, sp, #0 + lsls sp, r0, #0 + +// CHECK-THUMBV7: error: instruction variant requires ARMv8 or later +// CHECK-THUMBV7-NEXT: lsl sp, sp, #0 +// CHECK-THUMBV7: error: instruction variant requires ARMv8 or later +// CHECK-THUMBV7-NEXT: lsls sp, sp, #0 +// CHECK-THUMBV7: error: instruction variant requires ARMv8 or later +// CHECK-THUMBV7-NEXT: lsls r0, sp, #0 +// CHECK-THUMBV7: error: instruction variant requires ARMv8 or later +// CHECK-THUMBV7-NEXT: lsls sp, r0, #0 + +// CHECK-ARM: mov sp, sp @ encoding: [0x0d,0xd0,0xa0,0xe1] +// CHECK-ARM: movs sp, sp @ encoding: [0x0d,0xd0,0xb0,0xe1] +// CHECK-ARM: movs r0, sp @ encoding: [0x0d,0x00,0xb0,0xe1] +// CHECK-ARM: movs sp, r0 @ encoding: [0x00,0xd0,0xb0,0xe1] + + mov sp, sp, lsl #0 + movs sp, sp, lsl #0 + movs r0, sp, lsl #0 + movs sp, r0, lsl #0 + +// FIXME: We should consistently have the "requires ARMv8" error here +// CHECK-THUMBV7: error: invalid operand for instruction +// CHECK-THUMBV7-NEXT: mov sp, sp, lsl #0 +// CHECK-THUMBV7: error: invalid operand for instruction +// CHECK-THUMBV7-NEXT: movs sp, sp, lsl #0 +// CHECK-THUMBV7: error: instruction variant requires ARMv8 or later +// CHECK-THUMBV7-NEXT: movs r0, sp, lsl #0 +// CHECK-THUMBV7: error: invalid operand for instruction +// CHECK-THUMBV7-NEXT: movs sp, r0, lsl #0 + +// CHECK-ARM: mov sp, sp @ encoding: [0x0d,0xd0,0xa0,0xe1] +// CHECK-ARM: movs sp, sp @ encoding: [0x0d,0xd0,0xb0,0xe1] +// CHECK-ARM: movs r0, sp @ encoding: [0x0d,0x00,0xb0,0xe1] +// CHECK-ARM: movs sp, r0 @ encoding: [0x00,0xd0,0xb0,0xe1] diff --git a/test/MC/ARM/lsl-zero.s b/test/MC/ARM/lsl-zero.s index 02d094c8521..5d097115448 100644 --- a/test/MC/ARM/lsl-zero.s +++ b/test/MC/ARM/lsl-zero.s @@ -1,108 +1,11 @@ -// RUN: not llvm-mc -triple=thumbv7 -show-encoding < %s 2>&1 | FileCheck --check-prefix=CHECK --check-prefix=CHECK-NONARM --check-prefix=CHECK-THUMBV7 %s -// RUN: not llvm-mc -triple=thumbv8 -show-encoding < %s 2>&1 | FileCheck --check-prefix=CHECK --check-prefix=CHECK-NONARM --check-prefix=CHECK-THUMBV8 %s +// RUN: llvm-mc -triple=thumbv7 -show-encoding < %s 2>&1 | FileCheck --check-prefix=CHECK --check-prefix=CHECK-NONARM --check-prefix=CHECK-THUMBV7 %s +// RUN: llvm-mc -triple=thumbv8 -show-encoding < %s 2>&1 | FileCheck --check-prefix=CHECK --check-prefix=CHECK-NONARM --check-prefix=CHECK-THUMBV8 %s // RUN: llvm-mc -triple=armv7 -show-encoding < %s 2>&1 | FileCheck --check-prefix=CHECK --check-prefix=CHECK-ARM %s // lsl #0 is actually mov, so here we check that it behaves the same as // mov with regards to the permitted registers and how it behaves in an // IT block. - // Using PC is invalid in thumb - lsl pc, r0, #0 - lsl r0, pc, #0 - lsl pc, pc, #0 - lsls pc, r0, #0 - lsls r0, pc, #0 - lsls pc, pc, #0 - -// CHECK-NONARM: error: instruction requires: arm-mode -// CHECK-NONARM-NEXT: lsl pc, r0, #0 -// CHECK-NONARM: error: instruction requires: arm-mode -// CHECK-NONARM-NEXT: lsl r0, pc, #0 -// CHECK-NONARM: error: instruction requires: arm-mode -// CHECK-NONARM-NEXT: lsl pc, pc, #0 -// CHECK-NONARM: error: instruction requires: arm-mode -// CHECK-NONARM-NEXT: lsls pc, r0, #0 -// CHECK-NONARM: error: instruction requires: arm-mode -// CHECK-NONARM-NEXT: lsls r0, pc, #0 -// CHECK-NONARM: error: instruction requires: arm-mode -// CHECK-NONARM-NEXT: lsls pc, pc, #0 - -// CHECK-ARM: mov pc, r0 @ encoding: [0x00,0xf0,0xa0,0xe1] -// CHECK-ARM: mov r0, pc @ encoding: [0x0f,0x00,0xa0,0xe1] -// CHECK-ARM: mov pc, pc @ encoding: [0x0f,0xf0,0xa0,0xe1] -// CHECK-ARM: movs pc, r0 @ encoding: [0x00,0xf0,0xb0,0xe1] -// CHECK-ARM: movs r0, pc @ encoding: [0x0f,0x00,0xb0,0xe1] -// CHECK-ARM: movs pc, pc @ encoding: [0x0f,0xf0,0xb0,0xe1] - - mov pc, r0, lsl #0 - mov r0, pc, lsl #0 - mov pc, pc, lsl #0 - movs pc, r0, lsl #0 - movs r0, pc, lsl #0 - movs pc, pc, lsl #0 - -// FIXME: Really the error we should be giving is "requires: arm-mode" -// CHECK-NONARM: error: invalid operand for instruction -// CHECK-NONARM-NEXT: mov pc, r0, lsl #0 -// CHECK-NONARM: error: invalid operand for instruction -// CHECK-NONARM-NEXT: mov r0, pc, lsl #0 -// CHECK-NONARM: error: invalid operand for instruction -// CHECK-NONARM-NEXT: mov pc, pc, lsl #0 -// CHECK-NONARM: error: invalid operand for instruction -// CHECK-NONARM-NEXT: movs pc, r0, lsl #0 -// CHECK-NONARM: error: invalid operand for instruction -// CHECK-NONARM-NEXT: movs r0, pc, lsl #0 -// CHECK-NONARM: error: invalid operand for instruction -// CHECK-NONARM-NEXT: movs pc, pc, lsl #0 - -// CHECK-ARM: mov pc, r0 @ encoding: [0x00,0xf0,0xa0,0xe1] -// CHECK-ARM: mov r0, pc @ encoding: [0x0f,0x00,0xa0,0xe1] -// CHECK-ARM: mov pc, pc @ encoding: [0x0f,0xf0,0xa0,0xe1] -// CHECK-ARM: movs pc, r0 @ encoding: [0x00,0xf0,0xb0,0xe1] -// CHECK-ARM: movs r0, pc @ encoding: [0x0f,0x00,0xb0,0xe1] -// CHECK-ARM: movs pc, pc @ encoding: [0x0f,0xf0,0xb0,0xe1] - - // Using SP is invalid before ARMv8 in thumb unless non-flags-setting - // and one of the source and destination is not SP - lsl sp, sp, #0 - lsls sp, sp, #0 - lsls r0, sp, #0 - lsls sp, r0, #0 - -// CHECK-THUMBV7: error: instruction variant requires ARMv8 or later -// CHECK-THUMBV7-NEXT: lsl sp, sp, #0 -// CHECK-THUMBV7: error: instruction variant requires ARMv8 or later -// CHECK-THUMBV7-NEXT: lsls sp, sp, #0 -// CHECK-THUMBV7: error: instruction variant requires ARMv8 or later -// CHECK-THUMBV7-NEXT: lsls r0, sp, #0 -// CHECK-THUMBV7: error: instruction variant requires ARMv8 or later -// CHECK-THUMBV7-NEXT: lsls sp, r0, #0 - -// CHECK-ARM: mov sp, sp @ encoding: [0x0d,0xd0,0xa0,0xe1] -// CHECK-ARM: movs sp, sp @ encoding: [0x0d,0xd0,0xb0,0xe1] -// CHECK-ARM: movs r0, sp @ encoding: [0x0d,0x00,0xb0,0xe1] -// CHECK-ARM: movs sp, r0 @ encoding: [0x00,0xd0,0xb0,0xe1] - - mov sp, sp, lsl #0 - movs sp, sp, lsl #0 - movs r0, sp, lsl #0 - movs sp, r0, lsl #0 - -// FIXME: We should consistently have the "requires ARMv8" error here -// CHECK-THUMBV7: error: invalid operand for instruction -// CHECK-THUMBV7-NEXT: mov sp, sp, lsl #0 -// CHECK-THUMBV7: error: invalid operand for instruction -// CHECK-THUMBV7-NEXT: movs sp, sp, lsl #0 -// CHECK-THUMBV7: error: instruction variant requires ARMv8 or later -// CHECK-THUMBV7-NEXT: movs r0, sp, lsl #0 -// CHECK-THUMBV7: error: invalid operand for instruction -// CHECK-THUMBV7-NEXT: movs sp, r0, lsl #0 - -// CHECK-ARM: mov sp, sp @ encoding: [0x0d,0xd0,0xa0,0xe1] -// CHECK-ARM: movs sp, sp @ encoding: [0x0d,0xd0,0xb0,0xe1] -// CHECK-ARM: movs r0, sp @ encoding: [0x0d,0x00,0xb0,0xe1] -// CHECK-ARM: movs sp, r0 @ encoding: [0x00,0xd0,0xb0,0xe1] - // Non-flags-setting with only one of source and destination SP should // be OK lsl sp, r0, #0 -- 2.50.1