From a40de1884c10929b523e9919b0da04db44f8cfc2 Mon Sep 17 00:00:00 2001
From: Lewis Revill <lewis.revill@embecosm.com>
Date: Wed, 19 Jun 2019 10:27:24 +0000
Subject: [PATCH] [RISCV] Allow parsing immediates that use tilde & exclaim

This patch allows immediates (and CSR alias immediates) which start with
a tilde token or an exclaim (!) token to be parsed as intended.

Differential Revision: https://reviews.llvm.org/D57320


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363783 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp |  4 +++
 test/MC/RISCV/rv32i-valid.s                   | 30 +++++++++++++++++++
 2 files changed, 34 insertions(+)

diff --git a/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index 083d4b77ccc..f79cbd7fb6b 100644
--- a/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -1053,6 +1053,8 @@ RISCVAsmParser::parseCSRSystemRegister(OperandVector &Operands) {
   case AsmToken::LParen:
   case AsmToken::Minus:
   case AsmToken::Plus:
+  case AsmToken::Exclaim:
+  case AsmToken::Tilde:
   case AsmToken::Integer:
   case AsmToken::String: {
     if (getParser().parseExpression(Res))
@@ -1119,6 +1121,8 @@ OperandMatchResultTy RISCVAsmParser::parseImmediate(OperandVector &Operands) {
   case AsmToken::LParen:
   case AsmToken::Minus:
   case AsmToken::Plus:
+  case AsmToken::Exclaim:
+  case AsmToken::Tilde:
   case AsmToken::Integer:
   case AsmToken::String:
   case AsmToken::Identifier:
diff --git a/test/MC/RISCV/rv32i-valid.s b/test/MC/RISCV/rv32i-valid.s
index 7b711a32231..9571659b79b 100644
--- a/test/MC/RISCV/rv32i-valid.s
+++ b/test/MC/RISCV/rv32i-valid.s
@@ -96,6 +96,12 @@ jal s0, (0xff-99)
 jalr a0, a1, -2048
 # CHECK-ASM-AND-OBJ: jalr a0, a1, -2048
 # CHECK-ASM: encoding: [0x67,0x85,0x05,0x80]
+jalr a0, a1, ~2047
+# CHECK-ASM-AND-OBJ: jalr a0, a1, 0
+# CHECK-ASM: encoding: [0x67,0x85,0x05,0x00]
+jalr a0, a1, !1
+# CHECK-ASM-AND-OBJ: jalr a0, a1, -2048
+# CHECK-ASM: encoding: [0x67,0x85,0x05,0x80]
 jalr a0, a1, %lo(2048)
 # CHECK-ASM-AND-OBJ: jalr t2, t1, 2047
 # CHECK-ASM: encoding: [0xe7,0x03,0xf3,0x7f]
@@ -140,6 +146,12 @@ lb s3, +4(ra)
 lh t1, -2048(zero)
 # CHECK-ASM-AND-OBJ: lh t1, -2048(zero)
 # CHECK-ASM: encoding: [0x03,0x13,0x00,0x80]
+lh t1, ~2047(zero)
+# CHECK-ASM-AND-OBJ: lh t1, 0(zero)
+# CHECK-ASM: encoding: [0x03,0x13,0x00,0x00]
+lh t1, !1(zero)
+# CHECK-ASM-AND-OBJ: lh t1, -2048(zero)
+# CHECK-ASM: encoding: [0x03,0x13,0x00,0x80]
 lh t1, %lo(2048)(zero)
 # CHECK-ASM-AND-OBJ: lh sp, 2047(a0)
 # CHECK-ASM: encoding: [0x03,0x11,0xf5,0x7f]
@@ -175,6 +187,12 @@ sb a0, 2047(a2)
 sh t3, -2048(t5)
 # CHECK-ASM-AND-OBJ: sh t3, -2048(t5)
 # CHECK-ASM: encoding: [0x23,0x10,0xcf,0x81]
+sh t3, ~2047(t5)
+# CHECK-ASM-AND-OBJ: sh t3, 0(t5)
+# CHECK-ASM: encoding: [0x23,0x10,0xcf,0x01]
+sh t3, !1(t5)
+# CHECK-ASM-AND-OBJ: sh t3, -2048(t5)
+# CHECK-ASM: encoding: [0x23,0x10,0xcf,0x81]
 sh t3, %lo(2048)(t5)
 # CHECK-ASM-AND-OBJ: sw ra, 999(zero)
 # CHECK-ASM: encoding: [0xa3,0x23,0x10,0x3e]
@@ -220,6 +238,12 @@ xori tp, t1, -99
 ori a0, a1, -2048
 # CHECK-ASM-AND-OBJ: ori a0, a1, -2048
 # CHECK-ASM: encoding: [0x13,0xe5,0x05,0x80]
+ori a0, a1, ~2047
+# CHECK-ASM-AND-OBJ: ori a0, a1, 0
+# CHECK-ASM: encoding: [0x13,0xe5,0x05,0x00]
+ori a0, a1, !1
+# CHECK-ASM-AND-OBJ: ori a0, a1, -2048
+# CHECK-ASM: encoding: [0x13,0xe5,0x05,0x80]
 ori a0, a1, %lo(2048)
 # CHECK-ASM-AND-OBJ: andi ra, sp, 2047
 # CHECK-ASM: encoding: [0x93,0x70,0xf1,0x7f]
@@ -313,6 +337,12 @@ unimp
 # CHECK-ASM-AND-OBJ: csrrw t0, 4095, t1
 # CHECK-ASM: encoding: [0xf3,0x12,0xf3,0xff]
 csrrw t0, 0xfff, t1
+# CHECK-ASM-AND-OBJ: csrrw s0, 4095, s1
+# CHECK-ASM: encoding: [0x73,0x94,0xf4,0xff]
+csrrw s0, ~(-4096), s1
+# CHECK-ASM-AND-OBJ: csrrw s0, fflags, s1
+# CHECK-ASM: encoding: [0x73,0x94,0x14,0x00]
+csrrw s0, !0, s1
 # CHECK-ASM-AND-OBJ: csrrs s0, cycle, zero
 # CHECK-ASM: encoding: [0x73,0x24,0x00,0xc0]
 csrrs s0, 0xc00, x0
-- 
2.40.0