From a1a2854b18c6e270db74009cfc590dd22f8eae36 Mon Sep 17 00:00:00 2001 From: Sam Elliott Date: Wed, 7 Aug 2019 13:08:07 +0000 Subject: [PATCH] [RISCV][NFC] Document RISC-V-specific assembly constraints git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@368167 91177308-0d34-0410-b5e6-96231b3b80d8 --- docs/LangRef.rst | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/docs/LangRef.rst b/docs/LangRef.rst index abbd7941b5d..b6979e5fc2e 100644 --- a/docs/LangRef.rst +++ b/docs/LangRef.rst @@ -3952,6 +3952,17 @@ PowerPC: - ``ws``: A 32 or 64-bit floating-point register, from the full VSX register set. +RISC-V: + +- ``A``: An address operand (using a general-purpose register, without an + offset). +- ``I``: A 12-bit signed integer immediate operand. +- ``J``: A zero integer immediate operand. +- ``K``: A 5-bit unsigned integer immediate operand. +- ``f``: A 32- or 64-bit floating-point register (requires F or D extension). +- ``r``: A 32- or 64-bit general-purpose register (depending on the platform + ``XLEN``). + Sparc: - ``I``: An immediate 13-bit signed integer. -- 2.40.0