From a0e049148f8cb1501e6ec071027f5243a76be91b Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper@intel.com>
Date: Tue, 5 Feb 2019 06:13:06 +0000
Subject: [PATCH] [X86] Connect the default fpsr and dirflag clobbers in inline
 assembly to the registers we have defined for them.

Summary:
We don't currently map these constraints to physical register numbers so they don't make it to the MachineIR representation of inline assembly.

This could have problems for proper dependency tracking in the machine schedulers though I don't have a test case that shows that.

Reviewers: rnk

Reviewed By: rnk

Subscribers: eraman, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D57641

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@353141 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/X86/X86ISelLowering.cpp              | 8 ++++++++
 lib/Target/X86/X86RegisterInfo.td               | 2 +-
 test/CodeGen/X86/inline-asm-default-clobbers.ll | 8 ++++++++
 3 files changed, 17 insertions(+), 1 deletion(-)
 create mode 100644 test/CodeGen/X86/inline-asm-default-clobbers.ll

diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index 18cb4d1a2cb..314fed564c2 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -43006,6 +43006,14 @@ X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
     if (StringRef("{flags}").equals_lower(Constraint))
       return std::make_pair(X86::EFLAGS, &X86::CCRRegClass);
 
+    // dirflag -> DF
+    if (StringRef("{dirflag}").equals_lower(Constraint))
+      return std::make_pair(X86::DF, &X86::DFCCRRegClass);
+
+    // fpsr -> FPSW
+    if (StringRef("{fpsr}").equals_lower(Constraint))
+      return std::make_pair(X86::FPSW, &X86::FPCCRRegClass);
+
     // 'A' means [ER]AX + [ER]DX.
     if (Constraint == "A") {
       if (Subtarget.is64Bit())
diff --git a/lib/Target/X86/X86RegisterInfo.td b/lib/Target/X86/X86RegisterInfo.td
index 1deae9aa40d..50aa84ba284 100644
--- a/lib/Target/X86/X86RegisterInfo.td
+++ b/lib/Target/X86/X86RegisterInfo.td
@@ -287,7 +287,7 @@ def ST6 : X86Reg<"st(6)", 6>, DwarfRegNum<[39, 18, 17]>;
 def ST7 : X86Reg<"st(7)", 7>, DwarfRegNum<[40, 19, 18]>;
 
 // Floating-point status word
-def FPSW : X86Reg<"fpsw", 0>;
+def FPSW : X86Reg<"fpsr", 0>;
 
 // Status flags register.
 //
diff --git a/test/CodeGen/X86/inline-asm-default-clobbers.ll b/test/CodeGen/X86/inline-asm-default-clobbers.ll
new file mode 100644
index 00000000000..34a77ea5fec
--- /dev/null
+++ b/test/CodeGen/X86/inline-asm-default-clobbers.ll
@@ -0,0 +1,8 @@
+; RUN: llc < %s -mtriple=i686 -stop-after=expand-isel-pseudos | FileCheck %s
+
+; CHECK: INLINEASM &"", 1, 12, implicit-def early-clobber $df, 12, implicit-def early-clobber $fpsw, 12, implicit-def early-clobber $eflags
+define void @foo() {
+entry:
+  call void asm sideeffect "", "~{dirflag},~{fpsr},~{flags}"()
+  ret void
+}
-- 
2.50.1