From a0010d9f6bdbdd41d19213b7180853d03fc8d7bf Mon Sep 17 00:00:00 2001 From: Daniel Sanders Date: Tue, 6 Dec 2016 11:33:04 +0000 Subject: [PATCH] [globalisel][aarch64] Prefix PartialMappingIdx enumerators with 'PMI_' to fit coding standards. This also stops things like 'None' polluting the llvm::AArch64 namespace. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288799 91177308-0d34-0410-b5e6-96231b3b80d8 --- .../AArch64/AArch64GenRegisterBankInfo.def | 32 +++--- .../AArch64/AArch64RegisterBankInfo.cpp | 104 +++++++++--------- 2 files changed, 70 insertions(+), 66 deletions(-) diff --git a/lib/Target/AArch64/AArch64GenRegisterBankInfo.def b/lib/Target/AArch64/AArch64GenRegisterBankInfo.def index 621bd14cc5f..6431e42c014 100644 --- a/lib/Target/AArch64/AArch64GenRegisterBankInfo.def +++ b/lib/Target/AArch64/AArch64GenRegisterBankInfo.def @@ -26,18 +26,18 @@ RegisterBank *RegBanks[] = {&GPRRegBank, &FPRRegBank, &CCRRegBank}; // PartialMappings. enum PartialMappingIdx { - None = -1, - GPR32 = 0, - GPR64, - FPR32, - FPR64, - FPR128, - FPR256, - FPR512, - FirstGPR = GPR32, - LastGPR = GPR64, - FirstFPR = FPR32, - LastFPR = FPR512 + PMI_None = -1, + PMI_GPR32 = 0, + PMI_GPR64, + PMI_FPR32, + PMI_FPR64, + PMI_FPR128, + PMI_FPR256, + PMI_FPR512, + PMI_FirstGPR = PMI_GPR32, + PMI_LastGPR = PMI_GPR64, + PMI_FirstFPR = PMI_FPR32, + PMI_LastFPR = PMI_FPR512 }; static unsigned getRegBankBaseIdxOffset(unsigned Size) { @@ -115,7 +115,7 @@ RegisterBankInfo::ValueMapping ValMappings[] { /// \pre \p RBIdx != PartialMappingIdx::None const RegisterBankInfo::ValueMapping * getValueMapping(PartialMappingIdx RBIdx, unsigned Size) { - assert(RBIdx != PartialMappingIdx::None && "No mapping needed for that"); + assert(RBIdx != PartialMappingIdx::PMI_None && "No mapping needed for that"); unsigned ValMappingIdx = First3OpsIdx + (RBIdx + getRegBankBaseIdxOffset(Size)) * ValueMappingIdx::DistanceBetweenRegBanks; @@ -133,14 +133,14 @@ getValueMapping(PartialMappingIdx RBIdx, unsigned Size) { /// otherwise it is on FPR. Same thing for \p SrcIsGPR. const RegisterBankInfo::ValueMapping * getCopyMapping(bool DstIsGPR, bool SrcIsGPR, unsigned Size) { - PartialMappingIdx DstRBIdx = DstIsGPR ? FirstGPR : FirstFPR; - PartialMappingIdx SrcRBIdx = SrcIsGPR ? FirstGPR : FirstFPR; + PartialMappingIdx DstRBIdx = DstIsGPR ? PMI_FirstGPR : PMI_FirstFPR; + PartialMappingIdx SrcRBIdx = SrcIsGPR ? PMI_FirstGPR : PMI_FirstFPR; if (DstRBIdx == SrcRBIdx) return getValueMapping(DstRBIdx, Size); assert(Size <= 64 && "GPR cannot handle that size"); unsigned ValMappingIdx = FirstCrossRegCpyIdx + - (DstRBIdx - FirstGPR + getRegBankBaseIdxOffset(Size)) * + (DstRBIdx - PMI_FirstGPR + getRegBankBaseIdxOffset(Size)) * ValueMappingIdx::DistanceBetweenCrossRegCpy; assert(ValMappingIdx >= AArch64::FirstCrossRegCpyIdx && ValMappingIdx <= AArch64::LastCrossRegCpyIdx && diff --git a/lib/Target/AArch64/AArch64RegisterBankInfo.cpp b/lib/Target/AArch64/AArch64RegisterBankInfo.cpp index fb03252219f..ee748ee68a2 100644 --- a/lib/Target/AArch64/AArch64RegisterBankInfo.cpp +++ b/lib/Target/AArch64/AArch64RegisterBankInfo.cpp @@ -83,32 +83,32 @@ AArch64RegisterBankInfo::AArch64RegisterBankInfo(const TargetRegisterInfo &TRI) // Check that the TableGen'ed like file is in sync we our expectations. // First, the Idx. - assert(AArch64::PartialMappingIdx::GPR32 == - AArch64::PartialMappingIdx::FirstGPR && + assert(AArch64::PartialMappingIdx::PMI_GPR32 == + AArch64::PartialMappingIdx::PMI_FirstGPR && "GPR32 index not first in the GPR list"); - assert(AArch64::PartialMappingIdx::GPR64 == - AArch64::PartialMappingIdx::LastGPR && + assert(AArch64::PartialMappingIdx::PMI_GPR64 == + AArch64::PartialMappingIdx::PMI_LastGPR && "GPR64 index not last in the GPR list"); - assert(AArch64::PartialMappingIdx::FirstGPR <= - AArch64::PartialMappingIdx::LastGPR && + assert(AArch64::PartialMappingIdx::PMI_FirstGPR <= + AArch64::PartialMappingIdx::PMI_LastGPR && "GPR list is backward"); - assert(AArch64::PartialMappingIdx::FPR32 == - AArch64::PartialMappingIdx::FirstFPR && + assert(AArch64::PartialMappingIdx::PMI_FPR32 == + AArch64::PartialMappingIdx::PMI_FirstFPR && "FPR32 index not first in the FPR list"); - assert(AArch64::PartialMappingIdx::FPR512 == - AArch64::PartialMappingIdx::LastFPR && + assert(AArch64::PartialMappingIdx::PMI_FPR512 == + AArch64::PartialMappingIdx::PMI_LastFPR && "FPR512 index not last in the FPR list"); - assert(AArch64::PartialMappingIdx::FirstFPR <= - AArch64::PartialMappingIdx::LastFPR && + assert(AArch64::PartialMappingIdx::PMI_FirstFPR <= + AArch64::PartialMappingIdx::PMI_LastFPR && "FPR list is backward"); - assert(AArch64::PartialMappingIdx::FPR32 + 1 == - AArch64::PartialMappingIdx::FPR64 && - AArch64::PartialMappingIdx::FPR64 + 1 == - AArch64::PartialMappingIdx::FPR128 && - AArch64::PartialMappingIdx::FPR128 + 1 == - AArch64::PartialMappingIdx::FPR256 && - AArch64::PartialMappingIdx::FPR256 + 1 == - AArch64::PartialMappingIdx::FPR512 && + assert(AArch64::PartialMappingIdx::PMI_FPR32 + 1 == + AArch64::PartialMappingIdx::PMI_FPR64 && + AArch64::PartialMappingIdx::PMI_FPR64 + 1 == + AArch64::PartialMappingIdx::PMI_FPR128 && + AArch64::PartialMappingIdx::PMI_FPR128 + 1 == + AArch64::PartialMappingIdx::PMI_FPR256 && + AArch64::PartialMappingIdx::PMI_FPR256 + 1 == + AArch64::PartialMappingIdx::PMI_FPR512 && "FPR indices not properly ordered"); // Now, the content. // Check partial mapping. @@ -121,22 +121,22 @@ AArch64RegisterBankInfo::AArch64RegisterBankInfo(const TargetRegisterInfo &TRI) Map.RegBank == &RB && #Idx " is incorrectly initialized"); \ } while (0) - CHECK_PARTIALMAP(GPR32, 0, 32, RBGPR); - CHECK_PARTIALMAP(GPR64, 0, 64, RBGPR); - CHECK_PARTIALMAP(FPR32, 0, 32, RBFPR); - CHECK_PARTIALMAP(FPR64, 0, 64, RBFPR); - CHECK_PARTIALMAP(FPR128, 0, 128, RBFPR); - CHECK_PARTIALMAP(FPR256, 0, 256, RBFPR); - CHECK_PARTIALMAP(FPR512, 0, 512, RBFPR); + CHECK_PARTIALMAP(PMI_GPR32, 0, 32, RBGPR); + CHECK_PARTIALMAP(PMI_GPR64, 0, 64, RBGPR); + CHECK_PARTIALMAP(PMI_FPR32, 0, 32, RBFPR); + CHECK_PARTIALMAP(PMI_FPR64, 0, 64, RBFPR); + CHECK_PARTIALMAP(PMI_FPR128, 0, 128, RBFPR); + CHECK_PARTIALMAP(PMI_FPR256, 0, 256, RBFPR); + CHECK_PARTIALMAP(PMI_FPR512, 0, 512, RBFPR); // Check value mapping. #define CHECK_VALUEMAP_IMPL(RBName, Size, Offset) \ do { \ AArch64::PartialMappingIdx PartialMapBaseIdx = \ - AArch64::PartialMappingIdx::RBName##Size; \ + AArch64::PartialMappingIdx::PMI_##RBName##Size; \ (void) PartialMapBaseIdx; \ const ValueMapping &Map = \ - AArch64::getValueMapping(AArch64::First##RBName, Size)[Offset]; \ + AArch64::getValueMapping(AArch64::PMI_First##RBName, Size)[Offset]; \ (void) Map; \ assert(Map.BreakDown == &AArch64::PartMappings[PartialMapBaseIdx] && \ Map.NumBreakDowns == 1 && #RBName #Size \ @@ -173,14 +173,14 @@ AArch64RegisterBankInfo::AArch64RegisterBankInfo(const TargetRegisterInfo &TRI) #define CHECK_VALUEMAP_CROSSREGCPY(RBNameDst, RBNameSrc, Size) \ do { \ AArch64::PartialMappingIdx PartialMapDstIdx = \ - AArch64::PartialMappingIdx::RBNameDst##Size; \ + AArch64::PartialMappingIdx::PMI_##RBNameDst##Size; \ AArch64::PartialMappingIdx PartialMapSrcIdx = \ - AArch64::PartialMappingIdx::RBNameSrc##Size; \ + AArch64::PartialMappingIdx::PMI_##RBNameSrc##Size; \ (void) PartialMapDstIdx; \ (void) PartialMapSrcIdx; \ const ValueMapping *Map = AArch64::getCopyMapping( \ - AArch64::First##RBNameDst == AArch64::FirstGPR, \ - AArch64::First##RBNameSrc == AArch64::FirstGPR, Size); \ + AArch64::PMI_First##RBNameDst == AArch64::PMI_FirstGPR, \ + AArch64::PMI_First##RBNameSrc == AArch64::PMI_FirstGPR, Size); \ (void) Map; \ assert(Map[0].BreakDown == &AArch64::PartMappings[PartialMapDstIdx] && \ Map[0].NumBreakDowns == 1 && #RBNameDst #Size \ @@ -283,10 +283,12 @@ AArch64RegisterBankInfo::getInstrAlternativeMappings( break; InstructionMappings AltMappings; InstructionMapping GPRMapping( - /*ID*/ 1, /*Cost*/ 1, AArch64::getValueMapping(AArch64::FirstGPR, Size), + /*ID*/ 1, /*Cost*/ 1, + AArch64::getValueMapping(AArch64::PMI_FirstGPR, Size), /*NumOperands*/ 3); InstructionMapping FPRMapping( - /*ID*/ 2, /*Cost*/ 1, AArch64::getValueMapping(AArch64::FirstFPR, Size), + /*ID*/ 2, /*Cost*/ 1, + AArch64::getValueMapping(AArch64::PMI_FirstFPR, Size), /*NumOperands*/ 3); AltMappings.emplace_back(std::move(GPRMapping)); @@ -342,15 +344,17 @@ AArch64RegisterBankInfo::getInstrAlternativeMappings( InstructionMappings AltMappings; InstructionMapping GPRMapping( /*ID*/ 1, /*Cost*/ 1, - getOperandsMapping({AArch64::getValueMapping(AArch64::FirstGPR, Size), - // Addresses are GPR 64-bit. - AArch64::getValueMapping(AArch64::FirstGPR, 64)}), + getOperandsMapping( + {AArch64::getValueMapping(AArch64::PMI_FirstGPR, Size), + // Addresses are GPR 64-bit. + AArch64::getValueMapping(AArch64::PMI_FirstGPR, 64)}), /*NumOperands*/ 2); InstructionMapping FPRMapping( /*ID*/ 2, /*Cost*/ 1, - getOperandsMapping({AArch64::getValueMapping(AArch64::FirstFPR, Size), - // Addresses are GPR 64-bit. - AArch64::getValueMapping(AArch64::FirstGPR, 64)}), + getOperandsMapping( + {AArch64::getValueMapping(AArch64::PMI_FirstFPR, Size), + // Addresses are GPR 64-bit. + AArch64::getValueMapping(AArch64::PMI_FirstGPR, 64)}), /*NumOperands*/ 2); AltMappings.emplace_back(std::move(GPRMapping)); @@ -431,7 +435,7 @@ AArch64RegisterBankInfo::getSameKindOfOperandsMapping(const MachineInstr &MI) { #endif // End NDEBUG. AArch64::PartialMappingIdx RBIdx = - IsFPR ? AArch64::FirstFPR : AArch64::FirstGPR; + IsFPR ? AArch64::PMI_FirstFPR : AArch64::PMI_FirstGPR; return InstructionMapping{DefaultMappingID, 1, AArch64::getValueMapping(RBIdx, Size), NumOperands}; @@ -508,9 +512,9 @@ AArch64RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const { // As a top-level guess, vectors go in FPRs, scalars and pointers in GPRs. // For floating-point instructions, scalars go in FPRs. if (Ty.isVector() || isPreISelGenericFloatingPointOpcode(Opc)) - OpRegBankIdx[Idx] = AArch64::FirstFPR; + OpRegBankIdx[Idx] = AArch64::PMI_FirstFPR; else - OpRegBankIdx[Idx] = AArch64::FirstGPR; + OpRegBankIdx[Idx] = AArch64::PMI_FirstGPR; } unsigned Cost = 1; @@ -519,18 +523,18 @@ AArch64RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const { switch (Opc) { case TargetOpcode::G_SITOFP: case TargetOpcode::G_UITOFP: { - OpRegBankIdx = {AArch64::FirstFPR, AArch64::FirstGPR}; + OpRegBankIdx = {AArch64::PMI_FirstFPR, AArch64::PMI_FirstGPR}; break; } case TargetOpcode::G_FPTOSI: case TargetOpcode::G_FPTOUI: { - OpRegBankIdx = {AArch64::FirstGPR, AArch64::FirstFPR}; + OpRegBankIdx = {AArch64::PMI_FirstGPR, AArch64::PMI_FirstFPR}; break; } case TargetOpcode::G_FCMP: { - OpRegBankIdx = {AArch64::FirstGPR, - /* Predicate */ AArch64::PartialMappingIdx::None, - AArch64::FirstFPR, AArch64::FirstFPR}; + OpRegBankIdx = {AArch64::PMI_FirstGPR, + /* Predicate */ AArch64::PMI_None, AArch64::PMI_FirstFPR, + AArch64::PMI_FirstFPR}; break; } case TargetOpcode::G_BITCAST: { @@ -548,7 +552,7 @@ AArch64RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const { // for the greedy mode the cost of the cross bank copy will // offset this number. // FIXME: Should be derived from the scheduling model. - if (OpRegBankIdx[0] >= AArch64::FirstFPR) + if (OpRegBankIdx[0] >= AArch64::PMI_FirstFPR) Cost = 2; } } -- 2.50.1