From 9c924b4d86a4fcc02276ffe2761f5771efd956c4 Mon Sep 17 00:00:00 2001 From: Simon Atanasyan Date: Fri, 12 Jul 2019 04:58:45 +0000 Subject: [PATCH] [mips] Fix JmpLink to texternalsym and tglobaladdr on mcroMIPS R6 There is not match for the `MipsJmpLink texternalsym` and `MipsJmpLink tglobaladdr` patterns for microMIPS R6. As a result LLVM incorrectly selects the `JALRC16` compact 2-byte instruction which takes a target instruction address from a register only and assign `R_MIPS_32` relocation for this instruction. This relocation completely overwrites `JALRC16` and nearby instructions. This patch adds missed matching patterns, selects `BALC` instruction and assign a correct `R_MICROMIPS_PC26_S1` relocation. Differential Revision: https://reviews.llvm.org/D64552 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365870 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/MicroMips32r6InstrInfo.td | 13 +++++++++++++ lib/Target/Mips/MipsScheduleGeneric.td | 2 +- test/CodeGen/Mips/llvm-ir/fptosi.ll | 4 ++-- test/CodeGen/Mips/micromips-delay-slot.ll | 2 +- .../micromips-target-external-symbol-reloc.ll | 16 +++++++++++++--- test/CodeGen/Mips/tailcall/tailcall.ll | 18 +++++++++--------- 6 files changed, 39 insertions(+), 16 deletions(-) diff --git a/lib/Target/Mips/MicroMips32r6InstrInfo.td b/lib/Target/Mips/MicroMips32r6InstrInfo.td index dd86ba767b1..425773dc57f 100644 --- a/lib/Target/Mips/MicroMips32r6InstrInfo.td +++ b/lib/Target/Mips/MicroMips32r6InstrInfo.td @@ -1774,6 +1774,19 @@ let AddedComplexity = 41 in { def : StoreRegImmPat, FGR_64, ISA_MICROMIPS32R6; } +let isCall=1, hasDelaySlot=0, isCTI=1, Defs = [RA] in { + class JumpLinkMMR6 : + PseudoSE<(outs), (ins calltarget:$target), [], II_JAL>, + PseudoInstExpansion<(JumpInst Opnd:$target)>; +} + +def JAL_MMR6 : JumpLinkMMR6, ISA_MICROMIPS32R6; + +def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)), + (JAL_MMR6 texternalsym:$dst)>, ISA_MICROMIPS32R6; +def : MipsPat<(MipsJmpLink (iPTR tglobaladdr:$dst)), + (JAL_MMR6 tglobaladdr:$dst)>, ISA_MICROMIPS32R6; + def TAILCALL_MMR6 : TailCall, ISA_MICROMIPS32R6; def TAILCALLREG_MMR6 : TailCallReg, ISA_MICROMIPS32R6; diff --git a/lib/Target/Mips/MipsScheduleGeneric.td b/lib/Target/Mips/MipsScheduleGeneric.td index 10393280cf0..e8a0a30b8e9 100644 --- a/lib/Target/Mips/MipsScheduleGeneric.td +++ b/lib/Target/Mips/MipsScheduleGeneric.td @@ -384,7 +384,7 @@ def : InstRW<[GenericWriteJump], (instrs BC16_MMR6, BC1EQZC_MMR6, BC1NEZC_MMR6, BGTZC_MMR6, BLEZC_MMR6, BLTC_MMR6, BLTUC_MMR6, BLTZC_MMR6, BNEC_MMR6, BNEZC16_MMR6, BNEZC_MMR6, BNVC_MMR6, - BOVC_MMR6, DERET_MMR6, ERETNC_MMR6, + BOVC_MMR6, DERET_MMR6, ERETNC_MMR6, JAL_MMR6, ERET_MMR6, JIC_MMR6, JRADDIUSP, JRC16_MM, JRC16_MMR6, JRCADDIUSP_MMR6, SIGRIE_MMR6, B_MMR6_Pseudo, PseudoIndirectBranch_MMR6)>; diff --git a/test/CodeGen/Mips/llvm-ir/fptosi.ll b/test/CodeGen/Mips/llvm-ir/fptosi.ll index 6b4fd603056..3bf17abc796 100644 --- a/test/CodeGen/Mips/llvm-ir/fptosi.ll +++ b/test/CodeGen/Mips/llvm-ir/fptosi.ll @@ -208,7 +208,7 @@ define i32 @test1(float %t) { ; MMR6-SF-NEXT: # ; MMR6-SF-NEXT: # > ; MMR6-SF-NEXT: .cfi_offset 31, -4 -; MMR6-SF-NEXT: jalr __fixsfsi # > ; MMR6-SF-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload ; MMR6-SF-NEXT: # ; MMR6-SF-NEXT: # > ; MMR6-SF-NEXT: .cfi_offset 31, -4 -; MMR6-SF-NEXT: jalr __fixdfsi # > ; MMR6-SF-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload ; MMR6-SF-NEXT: #