From 9bb11013dd81086876d285d388edd52cab8b3c21 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Tue, 25 Jun 2019 13:23:08 +0000 Subject: [PATCH] AMDGPU/GlobalISel: Fix duplicated test Somehow ended up with copies of the same tests in AMDGPU and AMDGPU/GlobalISel git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364309 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/CodeGen/AMDGPU/inst-select-load-flat.mir | 28 --- test/CodeGen/AMDGPU/inst-select-load-smrd.mir | 159 ------------------ 2 files changed, 187 deletions(-) delete mode 100644 test/CodeGen/AMDGPU/inst-select-load-flat.mir delete mode 100644 test/CodeGen/AMDGPU/inst-select-load-smrd.mir diff --git a/test/CodeGen/AMDGPU/inst-select-load-flat.mir b/test/CodeGen/AMDGPU/inst-select-load-flat.mir deleted file mode 100644 index 31345a6e860..00000000000 --- a/test/CodeGen/AMDGPU/inst-select-load-flat.mir +++ /dev/null @@ -1,28 +0,0 @@ -# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=GCN -# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=GCN - -# REQUIRES: global-isel - ---- | - define amdgpu_kernel void @global_addrspace(i32 addrspace(1)* %global0) { ret void } -... ---- - -name: global_addrspace -legalized: true -regBankSelected: true - -# GCN: global_addrspace -# GCN: [[PTR:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 -# GCN: FLAT_LOAD_DWORD [[PTR]], 0, 0, 0, 0 - -body: | - bb.0: - liveins: $vgpr0_vgpr1 - - %0:vgpr(p1) = COPY $vgpr0_vgpr1 - %1:vgpr(s32) = G_LOAD %0 :: (load 4 from %ir.global0) - $vgpr0 = COPY %1 - -... ---- diff --git a/test/CodeGen/AMDGPU/inst-select-load-smrd.mir b/test/CodeGen/AMDGPU/inst-select-load-smrd.mir deleted file mode 100644 index e1f0f5c5fc9..00000000000 --- a/test/CodeGen/AMDGPU/inst-select-load-smrd.mir +++ /dev/null @@ -1,159 +0,0 @@ -# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=GCN,SI,SICI,SIVI -# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=GCN,CI,SICI -# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=GCN,VI,SIVI - -# REQUIRES: global-isel - ---- | - define amdgpu_kernel void @smrd_imm(i32 addrspace(4)* %const0) { ret void } -... ---- - -name: smrd_imm -legalized: true -regBankSelected: true - -# GCN: body: -# GCN: [[PTR:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1 - -# Immediate offset: -# SICI: S_LOAD_DWORD_IMM [[PTR]], 1, 0, 0 -# VI: S_LOAD_DWORD_IMM [[PTR]], 4, 0, 0 - -# Max immediate offset for SI -# SICI: S_LOAD_DWORD_IMM [[PTR]], 255, 0, 0 -# VI: S_LOAD_DWORD_IMM [[PTR]], 1020, 0, 0 - -# Immediate overflow for SI -# SI: [[K1024:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 1024 -# SI: S_LOAD_DWORD_SGPR [[PTR]], [[K1024]], 0 -# CI: S_LOAD_DWORD_IMM_ci [[PTR]], 256, 0 -# VI: S_LOAD_DWORD_IMM [[PTR]], 1024, 0 - -# Max immediate offset for VI -# SI: [[K1048572:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 1048572 -# CI: S_LOAD_DWORD_IMM_ci [[PTR]], 262143 -# VI: S_LOAD_DWORD_IMM [[PTR]], 1048572 - -# -# Immediate overflow for VI -# SIVI: [[K1048576:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 1048576 -# SIVI: S_LOAD_DWORD_SGPR [[PTR]], [[K1048576]], 0 -# CI: S_LOAD_DWORD_IMM_ci [[PTR]], 262144, 0 - -# Max immediate for CI -# SIVI: [[K_LO:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 4294967292 -# SIVI: [[K_HI:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 3 -# SIVI: [[K:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[K_LO]], %subreg.sub0, [[K_HI]], %subreg.sub1 -# SIVI-DAG: [[K_SUB0:%[0-9]+]]:sgpr_32 = COPY [[K]].sub0 -# SIVI-DAG: [[PTR_LO:%[0-9]+]]:sgpr_32 = COPY [[PTR]].sub0 -# SIVI: [[ADD_PTR_LO:%[0-9]+]]:sreg_32 = S_ADD_U32 [[PTR_LO]], [[K_SUB0]] -# SIVI-DAG: [[K_SUB1:%[0-9]+]]:sgpr_32 = COPY [[K]].sub1 -# SIVI-DAG: [[PTR_HI:%[0-9]+]]:sgpr_32 = COPY [[PTR]].sub1 -# SIVI: [[ADD_PTR_HI:%[0-9]+]]:sreg_32 = S_ADDC_U32 [[PTR_HI]], [[K_SUB1]] -# SIVI: [[ADD_PTR:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[ADD_PTR_LO]], %subreg.sub0, [[ADD_PTR_HI]], %subreg.sub1 -# SIVI: S_LOAD_DWORD_IMM [[ADD_PTR]], 0, 0, 0 -# CI: S_LOAD_DWORD_IMM_ci [[PTR]], 4294967295, 0, 0 - -# Immediate overflow for CI -# GCN: [[K_LO:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 0 -# GCN: [[K_HI:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 4 -# GCN: [[K:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[K_LO]], %subreg.sub0, [[K_HI]], %subreg.sub1 -# GCN-DAG: [[K_SUB0:%[0-9]+]]:sgpr_32 = COPY [[K]].sub0 -# GCN-DAG: [[PTR_LO:%[0-9]+]]:sgpr_32 = COPY [[PTR]].sub0 -# GCN: [[ADD_PTR_LO:%[0-9]+]]:sreg_32 = S_ADD_U32 [[PTR_LO]], [[K_SUB0]] -# GCN-DAG: [[K_SUB1:%[0-9]+]]:sgpr_32 = COPY [[K]].sub1 -# GCN-DAG: [[PTR_HI:%[0-9]+]]:sgpr_32 = COPY [[PTR]].sub1 -# GCN: [[ADD_PTR_HI:%[0-9]+]]:sreg_32 = S_ADDC_U32 [[PTR_HI]], [[K_SUB1]] -# GCN: [[ADD_PTR:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[ADD_PTR_LO]], %subreg.sub0, [[ADD_PTR_HI]], %subreg.sub1 -# GCN: S_LOAD_DWORD_IMM [[ADD_PTR]], 0, 0, 0 - -# Max 32-bit byte offset -# SIVI: [[K4294967292:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 4294967292 -# SIVI: S_LOAD_DWORD_SGPR [[PTR]], [[K4294967292]], 0 -# CI: S_LOAD_DWORD_IMM_ci [[PTR]], 1073741823, 0 - -# Overflow 32-bit byte offset -# SIVI: [[K_LO:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 0 -# SIVI: [[K_HI:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 1 -# SIVI: [[K:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[K_LO]], %subreg.sub0, [[K_HI]], %subreg.sub1 -# SIVI-DAG: [[K_SUB0:%[0-9]+]]:sgpr_32 = COPY [[K]].sub0 -# SIVI-DAG: [[PTR_LO:%[0-9]+]]:sgpr_32 = COPY [[PTR]].sub0 -# SIVI: [[ADD_PTR_LO:%[0-9]+]]:sreg_32 = S_ADD_U32 [[PTR_LO]], [[K_SUB0]] -# SIVI-DAG: [[K_SUB1:%[0-9]+]]:sgpr_32 = COPY [[K]].sub1 -# SIVI-DAG: [[PTR_HI:%[0-9]+]]:sgpr_32 = COPY [[PTR]].sub1 -# SIVI: [[ADD_PTR_HI:%[0-9]+]]:sreg_32 = S_ADDC_U32 [[PTR_HI]], [[K_SUB1]] -# SIVI: [[ADD_PTR:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[ADD_PTR_LO]], %subreg.sub0, [[ADD_PTR_HI]], %subreg.sub1 -# SIVI: S_LOAD_DWORD_IMM [[ADD_PTR]], 0, 0, 0 -# CI: S_LOAD_DWORD_IMM_ci [[PTR]], 1073741824, 0, 0 - -# Pointer loads -# GCN: [[AS0:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM %0 -# GCN: $sgpr0_sgpr1 = COPY [[AS0]] -# GCN: [[AS1:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM %0 -# GCN: $sgpr0_sgpr1 = COPY [[AS1]] -# GCN: [[AS4:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM %0 -# GCN: $sgpr0_sgpr1 = COPY [[AS4]] - -body: | - bb.0: - liveins: $sgpr0_sgpr1 - - %0:sgpr(p4) = COPY $sgpr0_sgpr1 - - %1:sgpr(s64) = G_CONSTANT i64 4 - %2:sgpr(p4) = G_GEP %0, %1 - %3:sgpr(s32) = G_LOAD %2 :: (load 4 from %ir.const0, addrspace 4) - $sgpr0 = COPY %3 - - %4:sgpr(s64) = G_CONSTANT i64 1020 - %5:sgpr(p4) = G_GEP %0, %4 - %6:sgpr(s32) = G_LOAD %5 :: (load 4 from %ir.const0, addrspace 4) - $sgpr0 = COPY %6 - - %7:sgpr(s64) = G_CONSTANT i64 1024 - %8:sgpr(p4) = G_GEP %0, %7 - %9:sgpr(s32) = G_LOAD %8 :: (load 4 from %ir.const0, addrspace 4) - $sgpr0 = COPY %9 - - %10:sgpr(s64) = G_CONSTANT i64 1048572 - %11:sgpr(p4) = G_GEP %0, %10 - %12:sgpr(s32) = G_LOAD %11 :: (load 4 from %ir.const0, addrspace 4) - $sgpr0 = COPY %12 - - %13:sgpr(s64) = G_CONSTANT i64 1048576 - %14:sgpr(p4) = G_GEP %0, %13 - %15:sgpr(s32) = G_LOAD %14 :: (load 4 from %ir.const0, addrspace 4) - $sgpr0 = COPY %15 - - %16:sgpr(s64) = G_CONSTANT i64 17179869180 - %17:sgpr(p4) = G_GEP %0, %16 - %18:sgpr(s32) = G_LOAD %17 :: (load 4 from %ir.const0, addrspace 4) - $sgpr0 = COPY %18 - - %19:sgpr(s64) = G_CONSTANT i64 17179869184 - %20:sgpr(p4) = G_GEP %0, %19 - %21:sgpr(s32) = G_LOAD %20 :: (load 4 from %ir.const0, addrspace 4) - $sgpr0 = COPY %21 - - %22:sgpr(s64) = G_CONSTANT i64 4294967292 - %23:sgpr(p4) = G_GEP %0, %22 - %24:sgpr(s32) = G_LOAD %23 :: (load 4 from %ir.const0, addrspace 4) - $sgpr0 = COPY %24 - - %25:sgpr(s64) = G_CONSTANT i64 4294967296 - %26:sgpr(p4) = G_GEP %0, %25 - %27:sgpr(s32) = G_LOAD %26 :: (load 4 from %ir.const0, addrspace 4) - $sgpr0 = COPY %27 - - %28:sgpr(p0) = G_LOAD %0 :: (load 8 from %ir.const0, addrspace 4) - $sgpr0_sgpr1 = COPY %28 - - %29:sgpr(p1) = G_LOAD %0 :: (load 8 from %ir.const0, addrspace 4) - $sgpr0_sgpr1 = COPY %29 - - %30:sgpr(p4) = G_LOAD %0 :: (load 8 from %ir.const0, addrspace 4) - $sgpr0_sgpr1 = COPY %30 - -... ---- -- 2.40.0