From 99a4c92625c344d81f22aaf12195221ee0a0136c Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Tue, 5 Mar 2019 18:54:38 +0000 Subject: [PATCH] [Subtarget] Merge ProcSched and ProcDesc arrays in MCSubtargetInfo into a single array. These arrays are both keyed by CPU name and go into the same tablegenerated file. Merge them so we only need to store keys once. This also removes a weird space saving quirk where we used the ProcDesc.size() to create to build an ArrayRef for ProcSched. Differential Revision: https://reviews.llvm.org/D58939 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355431 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/TargetSubtargetInfo.h | 1 - include/llvm/MC/MCSubtargetInfo.h | 21 +-------- lib/CodeGen/TargetSubtargetInfo.cpp | 4 +- lib/MC/MCSubtargetInfo.cpp | 20 ++++---- unittests/CodeGen/MachineInstrTest.cpp | 2 +- utils/TableGen/SubtargetEmitter.cpp | 53 +++++----------------- 6 files changed, 23 insertions(+), 78 deletions(-) diff --git a/include/llvm/CodeGen/TargetSubtargetInfo.h b/include/llvm/CodeGen/TargetSubtargetInfo.h index eb811de6426..9d502664852 100644 --- a/include/llvm/CodeGen/TargetSubtargetInfo.h +++ b/include/llvm/CodeGen/TargetSubtargetInfo.h @@ -64,7 +64,6 @@ protected: // Can only create subclasses... TargetSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS, ArrayRef PF, ArrayRef PD, - const SubtargetInfoKV *ProcSched, const MCWriteProcResEntry *WPR, const MCWriteLatencyEntry *WL, const MCReadAdvanceEntry *RA, const InstrStage *IS, diff --git a/include/llvm/MC/MCSubtargetInfo.h b/include/llvm/MC/MCSubtargetInfo.h index f784172ed0d..767a7abcbaf 100644 --- a/include/llvm/MC/MCSubtargetInfo.h +++ b/include/llvm/MC/MCSubtargetInfo.h @@ -54,6 +54,7 @@ struct SubtargetFeatureKV { struct SubtargetSubTypeKV { const char *Key; ///< K-V key string FeatureBitArray Implies; ///< K-V bit mask + const MCSchedModel *SchedModel; /// Compare routine for std::lower_bound bool operator<(StringRef S) const { @@ -66,24 +67,6 @@ struct SubtargetSubTypeKV { } }; -//===----------------------------------------------------------------------===// - -/// Used to provide key value pairs for CPU and arbitrary pointers. -struct SubtargetInfoKV { - const char *Key; ///< K-V key string - const void *Value; ///< K-V pointer value - - /// Compare routine for std::lower_bound - bool operator<(StringRef S) const { - return StringRef(Key) < S; - } - - /// Compare routine for std::is_sorted. - bool operator<(const SubtargetInfoKV &Other) const { - return StringRef(Key) < StringRef(Other.Key); - } -}; - //===----------------------------------------------------------------------===// /// /// Generic base class for all target subtargets. @@ -95,7 +78,6 @@ class MCSubtargetInfo { ArrayRef ProcDesc; // Processor descriptions // Scheduler machine model - const SubtargetInfoKV *ProcSchedModels; const MCWriteProcResEntry *WriteProcResTable; const MCWriteLatencyEntry *WriteLatencyTable; const MCReadAdvanceEntry *ReadAdvanceTable; @@ -111,7 +93,6 @@ public: MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS, ArrayRef PF, ArrayRef PD, - const SubtargetInfoKV *ProcSched, const MCWriteProcResEntry *WPR, const MCWriteLatencyEntry *WL, const MCReadAdvanceEntry *RA, const InstrStage *IS, const unsigned *OC, const unsigned *FP); diff --git a/lib/CodeGen/TargetSubtargetInfo.cpp b/lib/CodeGen/TargetSubtargetInfo.cpp index c0520a9b2ba..59eb2f9c88c 100644 --- a/lib/CodeGen/TargetSubtargetInfo.cpp +++ b/lib/CodeGen/TargetSubtargetInfo.cpp @@ -17,10 +17,10 @@ using namespace llvm; TargetSubtargetInfo::TargetSubtargetInfo( const Triple &TT, StringRef CPU, StringRef FS, ArrayRef PF, ArrayRef PD, - const SubtargetInfoKV *ProcSched, const MCWriteProcResEntry *WPR, + const MCWriteProcResEntry *WPR, const MCWriteLatencyEntry *WL, const MCReadAdvanceEntry *RA, const InstrStage *IS, const unsigned *OC, const unsigned *FP) - : MCSubtargetInfo(TT, CPU, FS, PF, PD, ProcSched, WPR, WL, RA, IS, OC, FP) { + : MCSubtargetInfo(TT, CPU, FS, PF, PD, WPR, WL, RA, IS, OC, FP) { } TargetSubtargetInfo::~TargetSubtargetInfo() = default; diff --git a/lib/MC/MCSubtargetInfo.cpp b/lib/MC/MCSubtargetInfo.cpp index ca174c735d2..2af8a5559b5 100644 --- a/lib/MC/MCSubtargetInfo.cpp +++ b/lib/MC/MCSubtargetInfo.cpp @@ -176,11 +176,11 @@ void MCSubtargetInfo::setDefaultFeatures(StringRef CPU, StringRef FS) { MCSubtargetInfo::MCSubtargetInfo( const Triple &TT, StringRef C, StringRef FS, ArrayRef PF, ArrayRef PD, - const SubtargetInfoKV *ProcSched, const MCWriteProcResEntry *WPR, + const MCWriteProcResEntry *WPR, const MCWriteLatencyEntry *WL, const MCReadAdvanceEntry *RA, const InstrStage *IS, const unsigned *OC, const unsigned *FP) : TargetTriple(TT), CPU(C), ProcFeatures(PF), ProcDesc(PD), - ProcSchedModels(ProcSched), WriteProcResTable(WPR), WriteLatencyTable(WL), + WriteProcResTable(WPR), WriteLatencyTable(WL), ReadAdvanceTable(RA), Stages(IS), OperandCycles(OC), ForwardingPaths(FP) { InitMCProcessorInfo(CPU, FS); } @@ -238,25 +238,21 @@ bool MCSubtargetInfo::checkFeatures(StringRef FS) const { } const MCSchedModel &MCSubtargetInfo::getSchedModelForCPU(StringRef CPU) const { - assert(ProcSchedModels && "Processor machine model not available!"); - - ArrayRef SchedModels(ProcSchedModels, ProcDesc.size()); - - assert(std::is_sorted(SchedModels.begin(), SchedModels.end()) && + assert(std::is_sorted(ProcDesc.begin(), ProcDesc.end()) && "Processor machine model table is not sorted"); // Find entry - auto Found = - std::lower_bound(SchedModels.begin(), SchedModels.end(), CPU); - if (Found == SchedModels.end() || StringRef(Found->Key) != CPU) { + const SubtargetSubTypeKV *CPUEntry = Find(CPU, ProcDesc); + + if (!CPUEntry) { if (CPU != "help") // Don't error if the user asked for help. errs() << "'" << CPU << "' is not a recognized processor for this target" << " (ignoring processor)\n"; return MCSchedModel::GetDefaultSchedModel(); } - assert(Found->Value && "Missing processor SchedModel value"); - return *(const MCSchedModel *)Found->Value; + assert(CPUEntry->SchedModel && "Missing processor SchedModel value"); + return *CPUEntry->SchedModel; } InstrItineraryData diff --git a/unittests/CodeGen/MachineInstrTest.cpp b/unittests/CodeGen/MachineInstrTest.cpp index 2678a4589f9..bfdd940bf37 100644 --- a/unittests/CodeGen/MachineInstrTest.cpp +++ b/unittests/CodeGen/MachineInstrTest.cpp @@ -47,7 +47,7 @@ class BogusSubtarget : public TargetSubtargetInfo { public: BogusSubtarget(TargetMachine &TM) : TargetSubtargetInfo(Triple(""), "", "", {}, {}, nullptr, nullptr, - nullptr, nullptr, nullptr, nullptr, nullptr), + nullptr, nullptr, nullptr, nullptr), FL(), TL(TM) {} ~BogusSubtarget() override {} diff --git a/utils/TableGen/SubtargetEmitter.cpp b/utils/TableGen/SubtargetEmitter.cpp index 198e5b4722b..9d134675fea 100644 --- a/utils/TableGen/SubtargetEmitter.cpp +++ b/utils/TableGen/SubtargetEmitter.cpp @@ -271,8 +271,10 @@ SubtargetEmitter::CPUKeyValues(raw_ostream &OS, printFeatureMask(OS, FeatureList, FeatureMap); - // The {{}} is for the "implies" section of this data structure. - OS << " },\n"; + // Emit the scheduler model pointer. + const std::string &ProcModelName = + SchedModels.getModelForProc(Processor).ModelName; + OS << ", &" << ProcModelName << " },\n"; } // End processor table @@ -1386,33 +1388,6 @@ void SubtargetEmitter::EmitProcessorModels(raw_ostream &OS) { } } -// -// EmitProcessorLookup - generate cpu name to sched model lookup tables. -// -void SubtargetEmitter::EmitProcessorLookup(raw_ostream &OS) { - // Gather and sort processor information - std::vector ProcessorList = - Records.getAllDerivedDefinitions("Processor"); - llvm::sort(ProcessorList, LessRecordFieldName()); - - // Begin processor->sched model table - OS << "\n"; - OS << "// Sorted (by key) array of sched model for CPU subtype.\n" - << "extern const llvm::SubtargetInfoKV " << Target - << "ProcSchedKV[] = {\n"; - // For each processor - for (Record *Processor : ProcessorList) { - StringRef Name = Processor->getValueAsString("Name"); - const std::string &ProcModelName = - SchedModels.getModelForProc(Processor).ModelName; - - // Emit as { "cpu", procinit }, - OS << " { \"" << Name << "\", (const void *)&" << ProcModelName << " },\n"; - } - // End processor->sched model table - OS << "};\n"; -} - // // EmitSchedModel - Emits all scheduling model tables, folding common patterns. // @@ -1441,12 +1416,10 @@ void SubtargetEmitter::EmitSchedModel(raw_ostream &OS) { } EmitSchedClassTables(SchedTables, OS); + OS << "\n#undef DBGFIELD\n"; + // Emit the processor machine model EmitProcessorModels(OS); - // Emit the processor lookup data - EmitProcessorLookup(OS); - - OS << "\n#undef DBGFIELD"; } static void emitPredicateProlog(const RecordKeeper &Records, raw_ostream &OS) { @@ -1759,12 +1732,11 @@ void SubtargetEmitter::emitGenMCSubtargetInfo(raw_ostream &OS) { OS << " " << Target << "GenMCSubtargetInfo(const Triple &TT, \n" << " StringRef CPU, StringRef FS, ArrayRef PF,\n" << " ArrayRef PD,\n" - << " const SubtargetInfoKV *ProcSched,\n" << " const MCWriteProcResEntry *WPR,\n" << " const MCWriteLatencyEntry *WL,\n" << " const MCReadAdvanceEntry *RA, const InstrStage *IS,\n" << " const unsigned *OC, const unsigned *FP) :\n" - << " MCSubtargetInfo(TT, CPU, FS, PF, PD, ProcSched,\n" + << " MCSubtargetInfo(TT, CPU, FS, PF, PD,\n" << " WPR, WL, RA, IS, OC, FP) { }\n\n" << " unsigned resolveVariantSchedClass(unsigned SchedClass,\n" << " const MCInst *MI, unsigned CPUID) const override {\n" @@ -1824,10 +1796,10 @@ void SubtargetEmitter::run(raw_ostream &OS) { #endif unsigned NumFeatures = FeatureKeyValues(OS, FeatureMap); OS << "\n"; - unsigned NumProcs = CPUKeyValues(OS, FeatureMap); - OS << "\n"; EmitSchedModel(OS); OS << "\n"; + unsigned NumProcs = CPUKeyValues(OS, FeatureMap); + OS << "\n"; #if 0 OS << "} // end anonymous namespace\n\n"; #endif @@ -1848,8 +1820,7 @@ void SubtargetEmitter::run(raw_ostream &OS) { else OS << "None, "; OS << '\n'; OS.indent(22); - OS << Target << "ProcSchedKV, " - << Target << "WriteProcResTable, " + OS << Target << "WriteProcResTable, " << Target << "WriteLatencyTable, " << Target << "ReadAdvanceTable, "; OS << '\n'; OS.indent(22); @@ -1916,7 +1887,6 @@ void SubtargetEmitter::run(raw_ostream &OS) { OS << "namespace llvm {\n"; OS << "extern const llvm::SubtargetFeatureKV " << Target << "FeatureKV[];\n"; OS << "extern const llvm::SubtargetSubTypeKV " << Target << "SubTypeKV[];\n"; - OS << "extern const llvm::SubtargetInfoKV " << Target << "ProcSchedKV[];\n"; OS << "extern const llvm::MCWriteProcResEntry " << Target << "WriteProcResTable[];\n"; OS << "extern const llvm::MCWriteLatencyEntry " @@ -1942,8 +1912,7 @@ void SubtargetEmitter::run(raw_ostream &OS) { else OS << "None, "; OS << '\n'; OS.indent(24); - OS << Target << "ProcSchedKV, " - << Target << "WriteProcResTable, " + OS << Target << "WriteProcResTable, " << Target << "WriteLatencyTable, " << Target << "ReadAdvanceTable, "; OS << '\n'; OS.indent(24); -- 2.50.1