From 9875a79d9f9adaa6fdad6ab70cedcdd7f2e26114 Mon Sep 17 00:00:00 2001
From: Guozhi Wei <carrot@google.com>
Date: Fri, 27 Oct 2017 21:54:24 +0000
Subject: [PATCH] [DAGCombine] Don't combine sext with extload if sextload is
 not supported and extload has multi users

In function DAGCombiner::visitSIGN_EXTEND_INREG, sext can be combined with extload even if sextload is not supported by target, then

  if sext is the only user of extload, there is no big difference, no harm no benefit.
  if extload has more than one user, the combined sextload may block extload from combining with other zext, causes extra zext instructions generated. As demonstrated by the attached test case.

This patch add the constraint that when sextload is not supported by target, sext can only be combined with extload if it is the only user of extload.

Differential Revision: https://reviews.llvm.org/D39108



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316802 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/CodeGen/SelectionDAG/DAGCombiner.cpp      |  6 ++++-
 test/CodeGen/PowerPC/selectiondag-sextload.ll | 26 +++++++++++++++++++
 2 files changed, 31 insertions(+), 1 deletion(-)
 create mode 100644 test/CodeGen/PowerPC/selectiondag-sextload.ll

diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index a64a79383d0..c75783af445 100644
--- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -8274,10 +8274,14 @@ SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
   }
 
   // fold (sext_inreg (extload x)) -> (sextload x)
+  // If sextload is not supported by target, we can only do the combine when
+  // load has one use. Doing otherwise can block folding the extload with other
+  // extends that the target does support.
   if (ISD::isEXTLoad(N0.getNode()) &&
       ISD::isUNINDEXEDLoad(N0.getNode()) &&
       EVT == cast<LoadSDNode>(N0)->getMemoryVT() &&
-      ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
+      ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile() &&
+        N0.hasOneUse()) ||
        TLI.isLoadExtLegal(ISD::SEXTLOAD, VT, EVT))) {
     LoadSDNode *LN0 = cast<LoadSDNode>(N0);
     SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, SDLoc(N), VT,
diff --git a/test/CodeGen/PowerPC/selectiondag-sextload.ll b/test/CodeGen/PowerPC/selectiondag-sextload.ll
new file mode 100644
index 00000000000..de33faf000a
--- /dev/null
+++ b/test/CodeGen/PowerPC/selectiondag-sextload.ll
@@ -0,0 +1,26 @@
+; RUN: llc --mtriple=powerpc64le-linux-gnu < %s | FileCheck %s
+
+; It tests in function DAGCombiner::visitSIGN_EXTEND_INREG
+; signext will not be combined with extload, and causes extra zext.
+
+declare void @g(i32 signext)
+
+define void @foo(i8* %p) {
+entry:
+  br label %while.body
+
+while.body:
+  %0 = load i8, i8* %p, align 1
+  %conv = zext i8 %0 to i32
+  %cmp = icmp sgt i8 %0, 0
+  br i1 %cmp, label %if.then, label %while.body
+; CHECK:     lbz
+; CHECK:     extsb.
+; CHECK-NOT: rlwinm
+; CHECK:     ble
+
+if.then:
+  tail call void @g(i32 signext %conv)
+  br label %while.body
+}
+
-- 
2.40.0