From 9556f6366cbdc75becc6520feb03ccf8532f56c1 Mon Sep 17 00:00:00 2001
From: Matt Arsenault <Matthew.Arsenault@amd.com>
Date: Fri, 4 Oct 2019 08:35:37 +0000
Subject: [PATCH] AMDGPU/GlobalISel: Select G_PTRTOINT
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@373715 91177308-0d34-0410-b5e6-96231b3b80d8
---
.../AMDGPU/AMDGPUInstructionSelector.cpp | 1 +
.../GlobalISel/inst-select-ptrtoint.mir | 101 ++++++++++++++++++
2 files changed, 102 insertions(+)
create mode 100644 test/CodeGen/AMDGPU/GlobalISel/inst-select-ptrtoint.mir
diff --git a/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
index c5e60ed77be..3adbeabc616 100644
--- a/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
+++ b/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
@@ -1670,6 +1670,7 @@ bool AMDGPUInstructionSelector::select(MachineInstr &I) {
return selectG_UADDO_USUBO(I);
case TargetOpcode::G_INTTOPTR:
case TargetOpcode::G_BITCAST:
+ case TargetOpcode::G_PTRTOINT:
return selectCOPY(I);
case TargetOpcode::G_CONSTANT:
case TargetOpcode::G_FCONSTANT:
diff --git a/test/CodeGen/AMDGPU/GlobalISel/inst-select-ptrtoint.mir b/test/CodeGen/AMDGPU/GlobalISel/inst-select-ptrtoint.mir
new file mode 100644
index 00000000000..53bd5e12a45
--- /dev/null
+++ b/test/CodeGen/AMDGPU/GlobalISel/inst-select-ptrtoint.mir
@@ -0,0 +1,101 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
+---
+
+name: ptrtoint_s_p3_to_s_s32
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0
+
+ ; CHECK-LABEL: name: ptrtoint_s_p3_to_s_s32
+ ; CHECK: liveins: $sgpr0
+ ; CHECK: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
+ ; CHECK: S_ENDPGM 0, implicit [[COPY]]
+ %0:sgpr(p3) = COPY $sgpr0
+ %1:sgpr(s32) = G_PTRTOINT %0
+ S_ENDPGM 0, implicit %1
+...
+
+---
+
+name: ptrtoint_s_p5_to_s_s32
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0
+
+ ; CHECK-LABEL: name: ptrtoint_s_p5_to_s_s32
+ ; CHECK: liveins: $sgpr0
+ ; CHECK: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
+ ; CHECK: S_ENDPGM 0, implicit [[COPY]]
+ %0:sgpr(p5) = COPY $sgpr0
+ %1:sgpr(s32) = G_PTRTOINT %0
+ S_ENDPGM 0, implicit %1
+...
+
+---
+
+name: ptrtoint_s_p0_to_s_s64
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0_sgpr1
+
+ ; CHECK-LABEL: name: ptrtoint_s_p0_to_s_s64
+ ; CHECK: liveins: $sgpr0_sgpr1
+ ; CHECK: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
+ ; CHECK: S_ENDPGM 0, implicit [[COPY]]
+ %0:sgpr(p0) = COPY $sgpr0_sgpr1
+ %1:sgpr(s64) = G_PTRTOINT %0
+ S_ENDPGM 0, implicit %1
+...
+
+---
+
+name: ptrtoint_s_p1_to_s_s64
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0_sgpr1
+
+ ; CHECK-LABEL: name: ptrtoint_s_p1_to_s_s64
+ ; CHECK: liveins: $sgpr0_sgpr1
+ ; CHECK: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
+ ; CHECK: S_ENDPGM 0, implicit [[COPY]]
+ %0:sgpr(p1) = COPY $sgpr0_sgpr1
+ %1:sgpr(s64) = G_PTRTOINT %0
+ S_ENDPGM 0, implicit %1
+...
+
+---
+
+name: ptrtoint_s_p999_to_s_s64
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0_sgpr1
+
+ ; CHECK-LABEL: name: ptrtoint_s_p999_to_s_s64
+ ; CHECK: liveins: $sgpr0_sgpr1
+ ; CHECK: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
+ ; CHECK: S_ENDPGM 0, implicit [[COPY]]
+ %0:sgpr(p999) = COPY $sgpr0_sgpr1
+ %1:sgpr(s64) = G_PTRTOINT %0
+ S_ENDPGM 0, implicit %1
+...
--
2.40.0