From 93efc10cbc897dfa9dd8066316c671989af857c3 Mon Sep 17 00:00:00 2001 From: Daniel Sanders Date: Wed, 28 Jun 2017 13:50:04 +0000 Subject: [PATCH] [globalisel][tablegen] Multiple 80-col corrections. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@306544 91177308-0d34-0410-b5e6-96231b3b80d8 --- utils/TableGen/GlobalISelEmitter.cpp | 61 +++++++++++++++++++--------- 1 file changed, 41 insertions(+), 20 deletions(-) diff --git a/utils/TableGen/GlobalISelEmitter.cpp b/utils/TableGen/GlobalISelEmitter.cpp index 50da9085c21..79fb350ca34 100644 --- a/utils/TableGen/GlobalISelEmitter.cpp +++ b/utils/TableGen/GlobalISelEmitter.cpp @@ -80,8 +80,8 @@ public: return; } if (Ty.isVector()) { - OS << "LLT::vector(" << Ty.getNumElements() << ", " << Ty.getScalarSizeInBits() - << ")"; + OS << "LLT::vector(" << Ty.getNumElements() << ", " + << Ty.getScalarSizeInBits() << ")"; return; } llvm_unreachable("Unhandled LLT"); @@ -96,7 +96,8 @@ class InstructionMatcher; static Optional MVTToLLT(MVT::SimpleValueType SVT) { MVT VT(SVT); if (VT.isVector() && VT.getVectorNumElements() != 1) - return LLTCodeGen(LLT::vector(VT.getVectorNumElements(), VT.getScalarSizeInBits())); + return LLTCodeGen( + LLT::vector(VT.getVectorNumElements(), VT.getScalarSizeInBits())); if (VT.isInteger() || VT.isFloatingPoint()) return LLTCodeGen(LLT::scalar(VT.getSizeInBits())); return None; @@ -241,12 +242,18 @@ public: return *static_cast(Predicates.back().get()); } - typename PredicateVec::const_iterator predicates_begin() const { return Predicates.begin(); } - typename PredicateVec::const_iterator predicates_end() const { return Predicates.end(); } + typename PredicateVec::const_iterator predicates_begin() const { + return Predicates.begin(); + } + typename PredicateVec::const_iterator predicates_end() const { + return Predicates.end(); + } iterator_range predicates() const { return make_range(predicates_begin(), predicates_end()); } - typename PredicateVec::size_type predicates_size() const { return Predicates.size(); } + typename PredicateVec::size_type predicates_size() const { + return Predicates.size(); + } /// Emit a C++ expression that tests whether all the predicates are met. template @@ -600,7 +607,8 @@ public: /// Compare the priority of this object and B. /// /// Returns true if this object is more important than B. - virtual bool isHigherPriorityThan(const InstructionPredicateMatcher &B) const { + virtual bool + isHigherPriorityThan(const InstructionPredicateMatcher &B) const { return Kind < B.Kind; }; @@ -631,7 +639,8 @@ public: /// Compare the priority of this object and B. /// /// Returns true if this object is more important than B. - bool isHigherPriorityThan(const InstructionPredicateMatcher &B) const override { + bool + isHigherPriorityThan(const InstructionPredicateMatcher &B) const override { if (InstructionPredicateMatcher::isHigherPriorityThan(B)) return true; if (B.InstructionPredicateMatcher::isHigherPriorityThan(*this)) @@ -1118,7 +1127,8 @@ public: void emitCxxActionStmts(raw_ostream &OS, RuleMatcher &Rule, StringRef RecycleVarName) const override { - OS << " constrainSelectedInstRegOperands(" << Name << ", TII, TRI, RBI);\n"; + OS << " constrainSelectedInstRegOperands(" << Name + << ", TII, TRI, RBI);\n"; } }; @@ -1165,14 +1175,16 @@ std::string RuleMatcher::defineInsnVar(raw_ostream &OS, return InsnVarName; } -StringRef RuleMatcher::getInsnVarName(const InstructionMatcher &InsnMatcher) const { +StringRef +RuleMatcher::getInsnVarName(const InstructionMatcher &InsnMatcher) const { const auto &I = InsnVariableNames.find(&InsnMatcher); if (I != InsnVariableNames.end()) return I->second; llvm_unreachable("Matched Insn was not captured in a local variable"); } -/// Emit a C++ initializer_list containing references to every matched instruction. +/// Emit a C++ initializer_list containing references to every matched +/// instruction. void RuleMatcher::emitCxxCapturedInsnList(raw_ostream &OS) { SmallVector Names; for (const auto &Pair : InsnVariableNames) @@ -1425,7 +1437,8 @@ Expected GlobalISelEmitter::createAndImportSelDAGMatcher( InsnMatcher.addPredicate( &Target.getInstruction(RK.getDef("G_CONSTANT"))); } else - return failedImport("Unable to deduce gMIR opcode to handle Src (which is a leaf)"); + return failedImport( + "Unable to deduce gMIR opcode to handle Src (which is a leaf)"); } else { auto SrcGIOrNull = findNodeEquiv(Src->getOperator()); if (!SrcGIOrNull) @@ -1458,7 +1471,8 @@ Expected GlobalISelEmitter::createAndImportSelDAGMatcher( OperandMatcher &OM = InsnMatcher.addOperand(OpIdx++, "", TempOpIdx); OM.addPredicate(SrcIntInit->getValue()); } else - return failedImport("Unable to deduce gMIR opcode to handle Src (which is a leaf)"); + return failedImport( + "Unable to deduce gMIR opcode to handle Src (which is a leaf)"); } else { // Match the used operands (i.e. the children of the operator). for (unsigned i = 0, e = Src->getNumChildren(); i != e; ++i) { @@ -1666,7 +1680,8 @@ Expected GlobalISelEmitter::createAndImportInstructionRenderer( if (!Dst->getChild(0)->isLeaf()) return failedImport("EXTRACT_SUBREG child #1 is not a leaf"); - if (DefInit *SubRegInit = dyn_cast(Dst->getChild(1)->getLeafValue())) { + if (DefInit *SubRegInit = + dyn_cast(Dst->getChild(1)->getLeafValue())) { CodeGenRegisterClass *RC = CGRegs.getRegClass( getInitValueAsRegClass(Dst->getChild(0)->getLeafValue())); CodeGenSubRegIndex *SubIdx = CGRegs.getSubRegIdx(SubRegInit->getDef()); @@ -1817,7 +1832,8 @@ Expected GlobalISelEmitter::runOnPattern(const PatternToMatch &P) { if (!Dst->getChild(0)->isLeaf()) return failedImport("EXTRACT_SUBREG operand #0 isn't a leaf"); - // We can assume that a subregister is in the same bank as it's super register. + // We can assume that a subregister is in the same bank as it's super + // register. DstIOpRec = getInitValueAsRegClass(Dst->getChild(0)->getLeafValue()); if (DstIOpRec == nullptr) @@ -1826,7 +1842,8 @@ Expected GlobalISelEmitter::runOnPattern(const PatternToMatch &P) { } else if (DstIOpRec->isSubClassOf("RegisterOperand")) DstIOpRec = DstIOpRec->getValueAsDef("RegClass"); else if (!DstIOpRec->isSubClassOf("RegisterClass")) - return failedImport("Dst MI def isn't a register class" + to_string(*Dst)); + return failedImport("Dst MI def isn't a register class" + + to_string(*Dst)); OperandMatcher &OM = InsnMatcher.getOperand(OpIdx); OM.setSymbolicName(DstIOperand.Name); @@ -1898,8 +1915,10 @@ Expected GlobalISelEmitter::runOnPattern(const PatternToMatch &P) { const auto &SrcRCDstRCPair = SrcRC->getMatchingSubClassWithSubRegs(CGRegs, SubIdx); assert(SrcRCDstRCPair->second && "Couldn't find a matching subclass"); - M.addAction("NewI", 0, *SrcRCDstRCPair->second); - M.addAction("NewI", 1, *SrcRCDstRCPair->first); + M.addAction("NewI", 0, + *SrcRCDstRCPair->second); + M.addAction("NewI", 1, + *SrcRCDstRCPair->first); // We're done with this pattern! It's eligible for GISel emission; return // it. @@ -2007,8 +2026,10 @@ void GlobalISelEmitter::run(raw_ostream &OS) { << "InstructionSelector::selectImpl(MachineInstr &I) const {\n" << " MachineFunction &MF = *I.getParent()->getParent();\n" << " const MachineRegisterInfo &MRI = MF.getRegInfo();\n" - << " // FIXME: This should be computed on a per-function basis rather than per-insn.\n" - << " AvailableFunctionFeatures = computeAvailableFunctionFeatures(&STI, &MF);\n" + << " // FIXME: This should be computed on a per-function basis rather " + "than per-insn.\n" + << " AvailableFunctionFeatures = computeAvailableFunctionFeatures(&STI, " + "&MF);\n" << " const PredicateBitset AvailableFeatures = getAvailableFeatures();\n"; for (auto &Rule : Rules) { -- 2.40.0