From 93cc33fa0ff4da73bcec44e7fb2f403bbdbce0e4 Mon Sep 17 00:00:00 2001 From: Jessica Paquette Date: Mon, 4 Feb 2019 17:32:47 +0000 Subject: [PATCH] Revert "[GlobalISel] Introduce a generic floating point floor opcode, G_FFLOOR" This reverts commit b05ecba6d687fcb3078509220c67458bf1d77a2e. Apparently adding floor breaks AMDGPU somehow, so I have to back this out while I look into it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@353065 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/Support/TargetOpcodes.def | 3 --- include/llvm/Target/GenericOpcodes.td | 7 ------- include/llvm/Target/GlobalISel/SelectionDAGCompat.td | 1 - .../AArch64/GlobalISel/legalizer-info-validation.mir | 5 +---- 4 files changed, 1 insertion(+), 15 deletions(-) diff --git a/include/llvm/Support/TargetOpcodes.def b/include/llvm/Support/TargetOpcodes.def index 5f4e9c67a09..23d008a0147 100644 --- a/include/llvm/Support/TargetOpcodes.def +++ b/include/llvm/Support/TargetOpcodes.def @@ -529,9 +529,6 @@ HANDLE_TARGET_OPCODE(G_FSIN) /// Floating point square root. HANDLE_TARGET_OPCODE(G_FSQRT) -/// Floating point floor. -HANDLE_TARGET_OPCODE(G_FFLOOR) - /// Generic AddressSpaceCast. HANDLE_TARGET_OPCODE(G_ADDRSPACE_CAST) diff --git a/include/llvm/Target/GenericOpcodes.td b/include/llvm/Target/GenericOpcodes.td index 41d1ed9937a..b61ed926501 100644 --- a/include/llvm/Target/GenericOpcodes.td +++ b/include/llvm/Target/GenericOpcodes.td @@ -579,13 +579,6 @@ def G_FSQRT : GenericInstruction { let hasSideEffects = 0; } -// Floating point floor of a value. -def G_FFLOOR : GenericInstruction { - let OutOperandList = (outs type0:$dst); - let InOperandList = (ins type0:$src1); - let hasSideEffects = 0; -} - //------------------------------------------------------------------------------ // Opcodes for LLVM Intrinsics //------------------------------------------------------------------------------ diff --git a/include/llvm/Target/GlobalISel/SelectionDAGCompat.td b/include/llvm/Target/GlobalISel/SelectionDAGCompat.td index 6b0434a0758..cbda4ab86a5 100644 --- a/include/llvm/Target/GlobalISel/SelectionDAGCompat.td +++ b/include/llvm/Target/GlobalISel/SelectionDAGCompat.td @@ -93,7 +93,6 @@ def : GINodeEquiv; def : GINodeEquiv; def : GINodeEquiv; def : GINodeEquiv; -def : GINodeEquiv; // Broadly speaking G_LOAD is equivalent to ISD::LOAD but there are some // complications that tablegen must take care of. For example, Predicates such diff --git a/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir b/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir index ab144eedfac..09574f0b85d 100644 --- a/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir +++ b/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir @@ -340,10 +340,7 @@ # DEBUG: .. the first uncovered type index: 1, OK # # DEBUG-NEXT: G_FSQRT (opcode {{[0-9]+}}): 1 type index -# DEBUG: .. type index coverage check SKIPPED: user-defined predicate detected -# -# DEBUG-NEXT: G_FFLOOR (opcode {{[0-9]+}}): 1 type index -# DEBUG: .. type index coverage check SKIPPED: no rules defined +# DEBUG: .. the first uncovered type index: 1, OK # CHECK-NOT: ill-defined -- 2.50.1