From 90c43ea95edd18726e28d2e1e88aed4160db8136 Mon Sep 17 00:00:00 2001 From: Ivan Grokhotkov Date: Wed, 18 Jan 2017 22:49:41 +0800 Subject: [PATCH] newlib: fix register used for DPORT/RTC bug workaround While there was no register at DR_REG_FRC_TIMER_BASE + 0x60, due to peripheral address space wraparound this write actually affected one of FRC2 registers, which is used by WiFi stack to implement legacy ets_timer APIs. This change uses FRC_TIMER_LOAD_REG(0) instead, which can be set to known value safely. --- components/newlib/time.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/components/newlib/time.c b/components/newlib/time.c index 30c7ca7f40..7595ab82b8 100644 --- a/components/newlib/time.c +++ b/components/newlib/time.c @@ -85,9 +85,8 @@ static void IRAM_ATTR frc_timer_isr() { // Write to FRC_TIMER_INT_REG may not take effect in some cases (root cause TBD) // This extra write works around this issue. - // There is no register at DR_REG_FRC_TIMER_BASE + 0x60 (in fact, any DPORT register address can be used). - WRITE_PERI_REG(DR_REG_FRC_TIMER_BASE + 0x60, 0xabababab); - // Clear interrupt status + // FRC_TIMER_LOAD_REG(0) is used here, but any other DPORT register address can also be used. + WRITE_PERI_REG(FRC_TIMER_LOAD_REG(0), FRC_TIMER_LOAD_VALUE(0)); WRITE_PERI_REG(FRC_TIMER_INT_REG(0), FRC_TIMER_INT_CLR); s_microseconds += FRC1_ISR_PERIOD_US; } -- 2.40.0