From 8fd05041c04936e2ec9ccd94e75e60ef7a3c1157 Mon Sep 17 00:00:00 2001 From: Eugene Zelenko Date: Mon, 11 Sep 2017 23:00:48 +0000 Subject: [PATCH] [CodeGen] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312971 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/MachineSSAUpdater.h | 36 ++++---- include/llvm/CodeGen/MachineTraceMetrics.h | 2 +- lib/CodeGen/MachinePipeliner.cpp | 99 +++++++++++----------- lib/CodeGen/MachineSSAUpdater.cpp | 36 +++++--- lib/CodeGen/MachineScheduler.cpp | 16 ++-- lib/CodeGen/MachineTraceMetrics.cpp | 5 +- lib/CodeGen/MachineVerifier.cpp | 90 +++++++++++++------- lib/CodeGen/OptimizePHIs.cpp | 22 +++-- lib/CodeGen/PHIElimination.cpp | 44 ++++++---- lib/CodeGen/PeepholeOptimizer.cpp | 59 ++++++++----- 10 files changed, 243 insertions(+), 166 deletions(-) diff --git a/include/llvm/CodeGen/MachineSSAUpdater.h b/include/llvm/CodeGen/MachineSSAUpdater.h index 50a7d90bf25..b5ea2080444 100644 --- a/include/llvm/CodeGen/MachineSSAUpdater.h +++ b/include/llvm/CodeGen/MachineSSAUpdater.h @@ -1,4 +1,4 @@ -//===-- MachineSSAUpdater.h - Unstructured SSA Update Tool ------*- C++ -*-===// +//===- MachineSSAUpdater.h - Unstructured SSA Update Tool -------*- C++ -*-===// // // The LLVM Compiler Infrastructure // @@ -14,18 +14,17 @@ #ifndef LLVM_CODEGEN_MACHINESSAUPDATER_H #define LLVM_CODEGEN_MACHINESSAUPDATER_H -#include "llvm/Support/Compiler.h" - namespace llvm { - class MachineBasicBlock; - class MachineFunction; - class MachineInstr; - class MachineOperand; - class MachineRegisterInfo; - class TargetInstrInfo; - class TargetRegisterClass; - template class SmallVectorImpl; - template class SSAUpdaterTraits; + +class MachineBasicBlock; +class MachineFunction; +class MachineInstr; +class MachineOperand; +class MachineRegisterInfo; +class TargetInstrInfo; +class TargetRegisterClass; +template class SmallVectorImpl; +template class SSAUpdaterTraits; /// MachineSSAUpdater - This class updates SSA form for a set of virtual /// registers defined in multiple blocks. This is used when code duplication @@ -38,7 +37,7 @@ private: /// AvailableVals - This keeps track of which value to use on a per-block /// basis. When we insert PHI nodes, we keep track of them here. //typedef DenseMap AvailableValsTy; - void *AV; + void *AV = nullptr; /// VR - Current virtual register whose uses are being updated. unsigned VR; @@ -52,11 +51,14 @@ private: const TargetInstrInfo *TII; MachineRegisterInfo *MRI; + public: /// MachineSSAUpdater constructor. If InsertedPHIs is specified, it will be /// filled in with all PHI Nodes created by rewriting. explicit MachineSSAUpdater(MachineFunction &MF, SmallVectorImpl *InsertedPHIs = nullptr); + MachineSSAUpdater(const MachineSSAUpdater &) = delete; + MachineSSAUpdater &operator=(const MachineSSAUpdater &) = delete; ~MachineSSAUpdater(); /// Initialize - Reset this object to get ready for a new set of SSA @@ -93,7 +95,6 @@ public: /// their respective blocks. However, the use of X happens in the *middle* of /// a block. Because of this, we need to insert a new PHI node in SomeBB to /// merge the appropriate values, and this value isn't live out of the block. - /// unsigned GetValueInMiddleOfBlock(MachineBasicBlock *BB); /// RewriteUse - Rewrite a use of the symbolic value. This handles PHI nodes, @@ -105,11 +106,8 @@ public: private: unsigned GetValueAtEndOfBlockInternal(MachineBasicBlock *BB); - - void operator=(const MachineSSAUpdater&) = delete; - MachineSSAUpdater(const MachineSSAUpdater&) = delete; }; -} // End llvm namespace +} // end namespace llvm -#endif +#endif // LLVM_CODEGEN_MACHINESSAUPDATER_H diff --git a/include/llvm/CodeGen/MachineTraceMetrics.h b/include/llvm/CodeGen/MachineTraceMetrics.h index 28f22f4d359..9d8db393ca9 100644 --- a/include/llvm/CodeGen/MachineTraceMetrics.h +++ b/include/llvm/CodeGen/MachineTraceMetrics.h @@ -52,13 +52,13 @@ #include "llvm/ADT/DenseMap.h" #include "llvm/ADT/None.h" #include "llvm/ADT/SmallVector.h" +#include "llvm/CodeGen/MachineBasicBlock.h" #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/TargetSchedule.h" namespace llvm { class AnalysisUsage; -class MachineBasicBlock; class MachineFunction; class MachineInstr; class MachineLoop; diff --git a/lib/CodeGen/MachinePipeliner.cpp b/lib/CodeGen/MachinePipeliner.cpp index 94ab062091e..91e1257ba4d 100644 --- a/lib/CodeGen/MachinePipeliner.cpp +++ b/lib/CodeGen/MachinePipeliner.cpp @@ -1,4 +1,4 @@ -//===-- MachinePipeliner.cpp - Machine Software Pipeliner Pass ------------===// +//===- MachinePipeliner.cpp - Machine Software Pipeliner Pass -------------===// // // The LLVM Compiler Infrastructure // @@ -80,7 +80,6 @@ #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineInstr.h" #include "llvm/CodeGen/MachineInstrBuilder.h" -#include "llvm/CodeGen/MachineInstrBundle.h" #include "llvm/CodeGen/MachineLoopInfo.h" #include "llvm/CodeGen/MachineMemOperand.h" #include "llvm/CodeGen/MachineOperand.h" @@ -92,15 +91,19 @@ #include "llvm/CodeGen/ScheduleDAGMutation.h" #include "llvm/IR/Attributes.h" #include "llvm/IR/DebugLoc.h" +#include "llvm/IR/Function.h" +#include "llvm/MC/LaneBitmask.h" +#include "llvm/MC/MCInstrDesc.h" #include "llvm/MC/MCInstrItineraries.h" -#include "llvm/PassAnalysisSupport.h" -#include "llvm/PassRegistry.h" -#include "llvm/PassSupport.h" +#include "llvm/MC/MCRegisterInfo.h" +#include "llvm/Pass.h" #include "llvm/Support/CommandLine.h" +#include "llvm/Support/Compiler.h" #include "llvm/Support/Debug.h" #include "llvm/Support/MathExtras.h" #include "llvm/Support/raw_ostream.h" #include "llvm/Target/TargetInstrInfo.h" +#include "llvm/Target/TargetOpcodes.h" #include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Target/TargetSubtargetInfo.h" #include @@ -111,6 +114,7 @@ #include #include #include +#include #include #include #include @@ -169,7 +173,6 @@ namespace { class NodeSet; class SMSchedule; -class SwingSchedulerDAG; /// The main class in the implementation of the target independent /// software pipeliner pass. @@ -185,6 +188,7 @@ public: #ifndef NDEBUG static int NumTries; #endif + /// Cache the target analysis information about the loop. struct LoopInfo { MachineBasicBlock *TBB = nullptr; @@ -196,6 +200,7 @@ public: LoopInfo LI; static char ID; + MachinePipeliner() : MachineFunctionPass(ID) { initializeMachinePipelinerPass(*PassRegistry::getPassRegistry()); } @@ -222,9 +227,9 @@ private: class SwingSchedulerDAG : public ScheduleDAGInstrs { MachinePipeliner &Pass; /// The minimum initiation interval between iterations for this schedule. - unsigned MII; + unsigned MII = 0; /// Set to true if a valid pipelined schedule is found for the loop. - bool Scheduled; + bool Scheduled = false; MachineLoop &Loop; LiveIntervals &LIS; const RegisterClassInfo &RegClassInfo; @@ -234,9 +239,10 @@ class SwingSchedulerDAG : public ScheduleDAGInstrs { ScheduleDAGTopologicalSort Topo; struct NodeInfo { - int ASAP; - int ALAP; - NodeInfo() : ASAP(0), ALAP(0) {} + int ASAP = 0; + int ALAP = 0; + + NodeInfo() = default; }; /// Computed properties for each node in the graph. std::vector ScheduleInfo; @@ -245,10 +251,10 @@ class SwingSchedulerDAG : public ScheduleDAGInstrs { /// Computed node ordering for scheduling. SetVector NodeOrder; - typedef SmallVector NodeSetType; - typedef DenseMap ValueMapTy; - typedef SmallVectorImpl MBBVectorTy; - typedef DenseMap InstrMapTy; + using NodeSetType = SmallVector; + using ValueMapTy = DenseMap; + using MBBVectorTy = SmallVectorImpl; + using InstrMapTy = DenseMap; /// Instructions to change when emitting the final schedule. DenseMap> InstrChanges; @@ -272,8 +278,8 @@ class SwingSchedulerDAG : public ScheduleDAGInstrs { public: Circuits(std::vector &SUs) - : SUnits(SUs), Stack(), Blocked(SUs.size()), B(SUs.size()), - AdjK(SUs.size()) {} + : SUnits(SUs), Blocked(SUs.size()), B(SUs.size()), AdjK(SUs.size()) {} + /// Reset the data structures used in the circuit algorithm. void reset() { Stack.clear(); @@ -281,6 +287,7 @@ class SwingSchedulerDAG : public ScheduleDAGInstrs { B.assign(SUnits.size(), SmallPtrSet()); NumPaths = 0; } + void createAdjacencyStructure(SwingSchedulerDAG *DAG); bool circuit(int V, int S, NodeSetType &NodeSets, bool HasBackedge = false); void unblock(int U); @@ -289,9 +296,8 @@ class SwingSchedulerDAG : public ScheduleDAGInstrs { public: SwingSchedulerDAG(MachinePipeliner &P, MachineLoop &L, LiveIntervals &lis, const RegisterClassInfo &rci) - : ScheduleDAGInstrs(*P.MF, P.MLI, false), Pass(P), MII(0), - Scheduled(false), Loop(L), LIS(lis), RegClassInfo(rci), - Topo(SUnits, &ExitSU) { + : ScheduleDAGInstrs(*P.MF, P.MLI, false), Pass(P), Loop(L), LIS(lis), + RegClassInfo(rci), Topo(SUnits, &ExitSU) { P.MF->getSubtarget().getSMSMutations(Mutations); } @@ -455,7 +461,7 @@ private: /// that assigns a priority to the set. class NodeSet { SetVector Nodes; - bool HasRecurrence; + bool HasRecurrence = false; unsigned RecMII = 0; int MaxMOV = 0; int MaxDepth = 0; @@ -463,10 +469,9 @@ class NodeSet { SUnit *ExceedPressure = nullptr; public: - typedef SetVector::const_iterator iterator; - - NodeSet() : Nodes(), HasRecurrence(false) {} + using iterator = SetVector::const_iterator; + NodeSet() = default; NodeSet(iterator S, iterator E) : Nodes(S, E), HasRecurrence(true) {} bool insert(SUnit *SU) { return Nodes.insert(SU); } @@ -581,13 +586,13 @@ private: /// Keep track of the first cycle value in the schedule. It starts /// as zero, but the algorithm allows negative values. - int FirstCycle; + int FirstCycle = 0; /// Keep track of the last cycle value in the schedule. - int LastCycle; + int LastCycle = 0; /// The initiation interval (II) for the schedule. - int InitiationInterval; + int InitiationInterval = 0; /// Target machine information. const TargetSubtargetInfo &ST; @@ -600,11 +605,7 @@ private: public: SMSchedule(MachineFunction *mf) : ST(mf->getSubtarget()), MRI(mf->getRegInfo()), - Resources(ST.getInstrInfo()->CreateTargetScheduleState(ST)) { - FirstCycle = 0; - LastCycle = 0; - InitiationInterval = 0; - } + Resources(ST.getInstrInfo()->CreateTargetScheduleState(ST)) {} void reset() { ScheduledInstrs.clear(); @@ -638,9 +639,9 @@ public: bool insert(SUnit *SU, int StartCycle, int EndCycle, int II); /// Iterators for the cycle to instruction map. - typedef DenseMap>::iterator sched_iterator; - typedef DenseMap>::const_iterator - const_sched_iterator; + using sched_iterator = DenseMap>::iterator; + using const_sched_iterator = + DenseMap>::const_iterator; /// Return true if the instruction is scheduled at the specified stage. bool isScheduledAtStage(SUnit *SU, unsigned StageNum) { @@ -715,6 +716,7 @@ char MachinePipeliner::ID = 0; int MachinePipeliner::NumTries = 0; #endif char &llvm::MachinePipelinerID = MachinePipeliner::ID; + INITIALIZE_PASS_BEGIN(MachinePipeliner, DEBUG_TYPE, "Modulo Software Pipelining", false, false) INITIALIZE_PASS_DEPENDENCY(AAResultsWrapperPass) @@ -1256,6 +1258,8 @@ struct FuncUnitSorter { const InstrItineraryData *InstrItins; DenseMap Resources; + FuncUnitSorter(const InstrItineraryData *IID) : InstrItins(IID) {} + // Compute the number of functional unit alternatives needed // at each stage, and take the minimum value. We prioritize the // instructions by the least number of choices first. @@ -1291,7 +1295,6 @@ struct FuncUnitSorter { } } - FuncUnitSorter(const InstrItineraryData *IID) : InstrItins(IID) {} /// Return true if IS1 has less priority than IS2. bool operator()(const MachineInstr *IS1, const MachineInstr *IS2) const { unsigned F1 = 0, F2 = 0; @@ -1384,7 +1387,7 @@ unsigned SwingSchedulerDAG::calculateRecMII(NodeSetType &NodeSets) { unsigned RecMII = 0; for (NodeSet &Nodes : NodeSets) { - if (Nodes.size() == 0) + if (Nodes.empty()) continue; unsigned Delay = Nodes.size() - 1; @@ -1554,7 +1557,6 @@ static bool ignoreDependence(const SDep &D, bool isPred) { /// D - Depth of each node. /// H - Height of each node. void SwingSchedulerDAG::computeNodeFunctions(NodeSetType &NodeSets) { - ScheduleInfo.resize(SUnits.size()); DEBUG({ @@ -1651,7 +1653,7 @@ static bool pred_L(SetVector &NodeOrder, Preds.insert(IS->getSUnit()); } } - return Preds.size() > 0; + return !Preds.empty(); } /// Compute the Succ_L(O) set, as defined in the paper. The set is defined @@ -1683,7 +1685,7 @@ static bool succ_L(SetVector &NodeOrder, Succs.insert(PI->getSUnit()); } } - return Succs.size() > 0; + return !Succs.empty(); } /// Return true if there is a path from the specified node to any of the nodes @@ -1868,7 +1870,7 @@ void SwingSchedulerDAG::groupRemainingNodes(NodeSetType &NodeSets) { Visited.clear(); computePath(NI, Path, NodesAdded, I, Visited); } - if (Path.size() > 0) + if (!Path.empty()) I.insert(Path.begin(), Path.end()); } // Add the nodes from the previous node set to the current node set. @@ -1879,7 +1881,7 @@ void SwingSchedulerDAG::groupRemainingNodes(NodeSetType &NodeSets) { Visited.clear(); computePath(NI, Path, I, NodesAdded, Visited); } - if (Path.size() > 0) + if (!Path.empty()) I.insert(Path.begin(), Path.end()); } NodesAdded.insert(I.begin(), I.end()); @@ -1892,7 +1894,7 @@ void SwingSchedulerDAG::groupRemainingNodes(NodeSetType &NodeSets) { if (succ_L(NodesAdded, N)) for (SUnit *I : N) addConnectedNodes(I, NewSet, NodesAdded); - if (NewSet.size() > 0) + if (!NewSet.empty()) NodeSets.push_back(NewSet); // Create a new node set with the connected nodes of any predecessor of a node @@ -1901,7 +1903,7 @@ void SwingSchedulerDAG::groupRemainingNodes(NodeSetType &NodeSets) { if (pred_L(NodesAdded, N)) for (SUnit *I : N) addConnectedNodes(I, NewSet, NodesAdded); - if (NewSet.size() > 0) + if (!NewSet.empty()) NodeSets.push_back(NewSet); // Create new nodes sets with the connected nodes any any remaining node that @@ -1911,7 +1913,7 @@ void SwingSchedulerDAG::groupRemainingNodes(NodeSetType &NodeSets) { if (NodesAdded.count(SU) == 0) { NewSet.clear(); addConnectedNodes(SU, NewSet, NodesAdded); - if (NewSet.size() > 0) + if (!NewSet.empty()) NodeSets.push_back(NewSet); } } @@ -1976,7 +1978,7 @@ void SwingSchedulerDAG::removeDuplicateNodes(NodeSetType &NodeSets) { for (NodeSetType::iterator J = I + 1; J != E;) { J->remove_if([&](SUnit *SUJ) { return I->count(SUJ); }); - if (J->size() == 0) { + if (J->empty()) { NodeSets.erase(J); E = NodeSets.end(); } else { @@ -2147,8 +2149,7 @@ void SwingSchedulerDAG::computeNodeOrder(NodeSetType &NodeSets) { /// Process the nodes in the computed order and create the pipelined schedule /// of the instructions, if possible. Return true if a schedule is found. bool SwingSchedulerDAG::schedulePipeline(SMSchedule &Schedule) { - - if (NodeOrder.size() == 0) + if (NodeOrder.empty()) return false; bool scheduleFound = false; @@ -2325,7 +2326,7 @@ void SwingSchedulerDAG::generateProlog(SMSchedule &Schedule, unsigned LastStage, ValueMapTy *VRMap, MBBVectorTy &PrologBBs) { MachineBasicBlock *PreheaderBB = MLI->getLoopFor(BB)->getLoopPreheader(); - assert(PreheaderBB != NULL && + assert(PreheaderBB != nullptr && "Need to add code to handle loops w/o preheader"); MachineBasicBlock *PredBB = PreheaderBB; InstrMapTy InstrMap; diff --git a/lib/CodeGen/MachineSSAUpdater.cpp b/lib/CodeGen/MachineSSAUpdater.cpp index e9b47559309..65d82366767 100644 --- a/lib/CodeGen/MachineSSAUpdater.cpp +++ b/lib/CodeGen/MachineSSAUpdater.cpp @@ -15,31 +15,36 @@ #include "llvm/CodeGen/MachineSSAUpdater.h" #include "llvm/ADT/DenseMap.h" #include "llvm/ADT/SmallVector.h" +#include "llvm/CodeGen/MachineBasicBlock.h" +#include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineInstr.h" #include "llvm/CodeGen/MachineInstrBuilder.h" +#include "llvm/CodeGen/MachineOperand.h" #include "llvm/CodeGen/MachineRegisterInfo.h" +#include "llvm/IR/DebugLoc.h" #include "llvm/Support/Debug.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/raw_ostream.h" #include "llvm/Target/TargetInstrInfo.h" -#include "llvm/Target/TargetRegisterInfo.h" +#include "llvm/Target/TargetOpcodes.h" #include "llvm/Target/TargetSubtargetInfo.h" #include "llvm/Transforms/Utils/SSAUpdaterImpl.h" +#include + using namespace llvm; #define DEBUG_TYPE "machine-ssaupdater" -typedef DenseMap AvailableValsTy; +using AvailableValsTy = DenseMap; + static AvailableValsTy &getAvailableVals(void *AV) { return *static_cast(AV); } MachineSSAUpdater::MachineSSAUpdater(MachineFunction &MF, SmallVectorImpl *NewPHI) - : AV(nullptr), InsertedPHIs(NewPHI) { - TII = MF.getSubtarget().getInstrInfo(); - MRI = &MF.getRegInfo(); -} + : InsertedPHIs(NewPHI), TII(MF.getSubtarget().getInstrInfo()), + MRI(&MF.getRegInfo()) {} MachineSSAUpdater::~MachineSSAUpdater() { delete static_cast(AV); @@ -77,7 +82,7 @@ unsigned MachineSSAUpdater::GetValueAtEndOfBlock(MachineBasicBlock *BB) { static unsigned LookForIdenticalPHI(MachineBasicBlock *BB, - SmallVectorImpl > &PredValues) { + SmallVectorImpl> &PredValues) { if (BB->empty()) return 0; @@ -136,7 +141,6 @@ MachineInstrBuilder InsertNewDef(unsigned Opcode, /// their respective blocks. However, the use of X happens in the *middle* of /// a block. Because of this, we need to insert a new PHI node in SomeBB to /// merge the appropriate values, and this value isn't live out of the block. -/// unsigned MachineSSAUpdater::GetValueInMiddleOfBlock(MachineBasicBlock *BB) { // If there is no definition of the renamed variable in this block, just use // GetValueAtEndOfBlock to do our work. @@ -233,14 +237,15 @@ void MachineSSAUpdater::RewriteUse(MachineOperand &U) { /// SSAUpdaterTraits - Traits for the SSAUpdaterImpl /// template, specialized for MachineSSAUpdater. namespace llvm { + template<> class SSAUpdaterTraits { public: - typedef MachineBasicBlock BlkT; - typedef unsigned ValT; - typedef MachineInstr PhiT; + using BlkT = MachineBasicBlock; + using ValT = unsigned; + using PhiT = MachineInstr; + using BlkSucc_iterator = MachineBasicBlock::succ_iterator; - typedef MachineBasicBlock::succ_iterator BlkSucc_iterator; static BlkSucc_iterator BlkSucc_begin(BlkT *BB) { return BB->succ_begin(); } static BlkSucc_iterator BlkSucc_end(BlkT *BB) { return BB->succ_end(); } @@ -259,12 +264,16 @@ public: PHI_iterator &operator++() { idx += 2; return *this; } bool operator==(const PHI_iterator& x) const { return idx == x.idx; } bool operator!=(const PHI_iterator& x) const { return !operator==(x); } + unsigned getIncomingValue() { return PHI->getOperand(idx).getReg(); } + MachineBasicBlock *getIncomingBlock() { return PHI->getOperand(idx+1).getMBB(); } }; + static inline PHI_iterator PHI_begin(PhiT *PHI) { return PHI_iterator(PHI); } + static inline PHI_iterator PHI_end(PhiT *PHI) { return PHI_iterator(PHI, true); } @@ -309,7 +318,6 @@ public: } /// InstrIsPHI - Check if an instruction is a PHI. - /// static MachineInstr *InstrIsPHI(MachineInstr *I) { if (I && I->isPHI()) return I; @@ -338,7 +346,7 @@ public: } }; -} // End llvm namespace +} // end namespace llvm /// GetValueAtEndOfBlockInternal - Check to see if AvailableVals has an entry /// for the specified BB and if so, return it. If not, construct SSA form by diff --git a/lib/CodeGen/MachineScheduler.cpp b/lib/CodeGen/MachineScheduler.cpp index 0257538e230..c64eccd286d 100644 --- a/lib/CodeGen/MachineScheduler.cpp +++ b/lib/CodeGen/MachineScheduler.cpp @@ -200,8 +200,7 @@ INITIALIZE_PASS_DEPENDENCY(LiveIntervals) INITIALIZE_PASS_END(MachineScheduler, DEBUG_TYPE, "Machine Instruction Scheduler", false, false) -MachineScheduler::MachineScheduler() -: MachineSchedulerBase(ID) { +MachineScheduler::MachineScheduler() : MachineSchedulerBase(ID) { initializeMachineSchedulerPass(*PassRegistry::getPassRegistry()); } @@ -225,8 +224,7 @@ char &llvm::PostMachineSchedulerID = PostMachineScheduler::ID; INITIALIZE_PASS(PostMachineScheduler, "postmisched", "PostRA Machine Instruction Scheduler", false, false) -PostMachineScheduler::PostMachineScheduler() -: MachineSchedulerBase(ID) { +PostMachineScheduler::PostMachineScheduler() : MachineSchedulerBase(ID) { initializePostMachineSchedulerPass(*PassRegistry::getPassRegistry()); } @@ -448,12 +446,14 @@ struct SchedRegion { MachineBasicBlock::iterator RegionBegin; MachineBasicBlock::iterator RegionEnd; unsigned NumRegionInstrs; + SchedRegion(MachineBasicBlock::iterator B, MachineBasicBlock::iterator E, unsigned N) : RegionBegin(B), RegionEnd(E), NumRegionInstrs(N) {} }; -typedef SmallVector MBBRegionsVector; +using MBBRegionsVector = SmallVector; + static void getSchedRegions(MachineBasicBlock *MBB, MBBRegionsVector &Regions, @@ -1589,7 +1589,6 @@ void BaseMemOpClusterMutation::clusterNeighboringMemOps( /// \brief Callback from DAG postProcessing to create cluster edges for loads. void BaseMemOpClusterMutation::apply(ScheduleDAGInstrs *DAGInstrs) { - ScheduleDAGMI *DAG = static_cast(DAGInstrs); // Map DAG NodeNum to store chain ID. @@ -1635,6 +1634,7 @@ namespace { class CopyConstrain : public ScheduleDAGMutation { // Transient state. SlotIndex RegionBeginIdx; + // RegionEndIdx is the slot index of the last non-debug instruction in the // scheduling region. So we may have RegionBeginIdx == RegionEndIdx. SlotIndex RegionEndIdx; @@ -3247,7 +3247,6 @@ void PostGenericScheduler::registerRoots() { /// \param TryCand refers to the next SUnit candidate, otherwise uninitialized. void PostGenericScheduler::tryCandidate(SchedCandidate &Cand, SchedCandidate &TryCand) { - // Initialize the candidate if needed. if (!Cand.isValid()) { TryCand.Reason = NodeOrder; @@ -3486,6 +3485,7 @@ class InstructionShuffler : public MachineSchedStrategy { // instructions to be scheduled first. PriorityQueue, SUnitOrder> TopQ; + // When scheduling bottom-up, use greater-than as the queue priority. PriorityQueue, SUnitOrder> BottomQ; @@ -3602,6 +3602,7 @@ struct DOTGraphTraits : public DefaultDOTGraphTraits { SS << " I:" << DFS->getNumInstrs(SU); return SS.str(); } + static std::string getNodeDescription(const SUnit *SU, const ScheduleDAG *G) { return G->getGraphNodeLabel(SU); } @@ -3625,7 +3626,6 @@ struct DOTGraphTraits : public DefaultDOTGraphTraits { /// viewGraph - Pop up a ghostview window with the reachable parts of the DAG /// rendered using 'dot'. -/// void ScheduleDAGMI::viewGraph(const Twine &Name, const Twine &Title) { #ifndef NDEBUG ViewGraph(this, Name, false, Title); diff --git a/lib/CodeGen/MachineTraceMetrics.cpp b/lib/CodeGen/MachineTraceMetrics.cpp index 534733edc7b..296f6001d21 100644 --- a/lib/CodeGen/MachineTraceMetrics.cpp +++ b/lib/CodeGen/MachineTraceMetrics.cpp @@ -22,13 +22,13 @@ #include "llvm/CodeGen/MachineLoopInfo.h" #include "llvm/CodeGen/MachineOperand.h" #include "llvm/CodeGen/MachineRegisterInfo.h" +#include "llvm/CodeGen/TargetSchedule.h" #include "llvm/MC/MCRegisterInfo.h" #include "llvm/Pass.h" #include "llvm/Support/Debug.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/Format.h" #include "llvm/Support/raw_ostream.h" -#include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Target/TargetSubtargetInfo.h" #include @@ -42,6 +42,7 @@ using namespace llvm; #define DEBUG_TYPE "machine-trace-metrics" char MachineTraceMetrics::ID = 0; + char &llvm::MachineTraceMetricsID = MachineTraceMetrics::ID; INITIALIZE_PASS_BEGIN(MachineTraceMetrics, DEBUG_TYPE, @@ -945,7 +946,7 @@ static unsigned updatePhysDepsUpwards(const MachineInstr &MI, unsigned Height, return Height; } -typedef DenseMap MIHeightMap; +using MIHeightMap = DenseMap; // Push the height of DefMI upwards if required to match UseMI. // Return true if this is the first time DefMI was seen. diff --git a/lib/CodeGen/MachineVerifier.cpp b/lib/CodeGen/MachineVerifier.cpp index 2ecfdd86793..0bd5c56871c 100644 --- a/lib/CodeGen/MachineVerifier.cpp +++ b/lib/CodeGen/MachineVerifier.cpp @@ -1,4 +1,4 @@ -//===-- MachineVerifier.cpp - Machine Code Verifier -----------------------===// +//===- MachineVerifier.cpp - Machine Code Verifier ------------------------===// // // The LLVM Compiler Infrastructure // @@ -23,41 +23,68 @@ // the verifier errors. //===----------------------------------------------------------------------===// +#include "llvm/ADT/BitVector.h" +#include "llvm/ADT/DenseMap.h" #include "llvm/ADT/DenseSet.h" #include "llvm/ADT/DepthFirstIterator.h" +#include "llvm/ADT/STLExtras.h" #include "llvm/ADT/SetOperations.h" +#include "llvm/ADT/SmallPtrSet.h" #include "llvm/ADT/SmallVector.h" +#include "llvm/ADT/StringRef.h" +#include "llvm/ADT/Twine.h" #include "llvm/Analysis/EHPersonalities.h" +#include "llvm/CodeGen/GlobalISel/RegisterBank.h" +#include "llvm/CodeGen/LiveInterval.h" #include "llvm/CodeGen/LiveIntervalAnalysis.h" #include "llvm/CodeGen/LiveStackAnalysis.h" #include "llvm/CodeGen/LiveVariables.h" +#include "llvm/CodeGen/MachineBasicBlock.h" #include "llvm/CodeGen/MachineFrameInfo.h" +#include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineFunctionPass.h" +#include "llvm/CodeGen/MachineInstr.h" +#include "llvm/CodeGen/MachineInstrBundle.h" #include "llvm/CodeGen/MachineMemOperand.h" +#include "llvm/CodeGen/MachineOperand.h" #include "llvm/CodeGen/MachineRegisterInfo.h" -#include "llvm/CodeGen/Passes.h" +#include "llvm/CodeGen/PseudoSourceValue.h" +#include "llvm/CodeGen/SlotIndexes.h" #include "llvm/CodeGen/StackMaps.h" #include "llvm/IR/BasicBlock.h" +#include "llvm/IR/Function.h" #include "llvm/IR/InlineAsm.h" #include "llvm/IR/Instructions.h" +#include "llvm/MC/LaneBitmask.h" #include "llvm/MC/MCAsmInfo.h" -#include "llvm/Support/Debug.h" +#include "llvm/MC/MCInstrDesc.h" +#include "llvm/MC/MCRegisterInfo.h" +#include "llvm/MC/MCTargetOptions.h" +#include "llvm/Pass.h" +#include "llvm/Support/Casting.h" #include "llvm/Support/ErrorHandling.h" -#include "llvm/Support/FileSystem.h" +#include "llvm/Support/LowLevelTypeImpl.h" +#include "llvm/Support/MathExtras.h" #include "llvm/Support/raw_ostream.h" #include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetMachine.h" +#include "llvm/Target/TargetOpcodes.h" #include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Target/TargetSubtargetInfo.h" +#include +#include +#include +#include +#include +#include +#include + using namespace llvm; namespace { - struct MachineVerifier { - MachineVerifier(Pass *pass, const char *b) : - PASS(pass), - Banner(b) - {} + struct MachineVerifier { + MachineVerifier(Pass *pass, const char *b) : PASS(pass), Banner(b) {} unsigned verify(MachineFunction &MF); @@ -75,11 +102,11 @@ namespace { bool isFunctionRegBankSelected; bool isFunctionSelected; - typedef SmallVector RegVector; - typedef SmallVector RegMaskVector; - typedef DenseSet RegSet; - typedef DenseMap RegMap; - typedef SmallPtrSet BlockSet; + using RegVector = SmallVector; + using RegMaskVector = SmallVector; + using RegSet = DenseSet; + using RegMap = DenseMap; + using BlockSet = SmallPtrSet; const MachineInstr *FirstTerminator; BlockSet FunctionBlocks; @@ -101,7 +128,7 @@ namespace { struct BBInfo { // Is this MBB reachable from the MF entry point? - bool reachable; + bool reachable = false; // Vregs that must be live in because they are used without being // defined. Map value is the user. @@ -126,7 +153,7 @@ namespace { // Set versions of block's predecessor and successor lists. BlockSet Preds, Succs; - BBInfo() : reachable(false) {} + BBInfo() = default; // Add register to vregsPassed if it belongs there. Return true if // anything changed. @@ -259,6 +286,7 @@ namespace { struct MachineVerifierPass : public MachineFunctionPass { static char ID; // Pass ID, replacement for typeid + const std::string Banner; MachineVerifierPass(std::string banner = std::string()) @@ -279,9 +307,10 @@ namespace { } }; -} +} // end anonymous namespace char MachineVerifierPass::ID = 0; + INITIALIZE_PASS(MachineVerifierPass, "machineverifier", "Verify generated machine code", false, false) @@ -1466,8 +1495,7 @@ void MachineVerifier::checkLiveness(const MachineOperand *MO, unsigned MONum) { } } -void MachineVerifier::visitMachineInstrAfter(const MachineInstr *MI) { -} +void MachineVerifier::visitMachineInstrAfter(const MachineInstr *MI) {} // This function gets called after visiting all instructions in a bundle. The // argument points to the bundle header. @@ -1952,7 +1980,7 @@ void MachineVerifier::verifyLiveRangeSegment(const LiveRange &LR, // Skip this block. ++MFI; } - for (;;) { + while (true) { assert(LiveInts->isLiveInToMBB(LR, &*MFI)); // We don't know how to track physregs into a landing pad. if (!TargetRegisterInfo::isVirtualRegister(Reg) && @@ -2058,23 +2086,25 @@ void MachineVerifier::verifyLiveInterval(const LiveInterval &LI) { } namespace { + // FrameSetup and FrameDestroy can have zero adjustment, so using a single // integer, we can't tell whether it is a FrameSetup or FrameDestroy if the // value is zero. // We use a bool plus an integer to capture the stack state. struct StackStateOfBB { - StackStateOfBB() : EntryValue(0), ExitValue(0), EntryIsSetup(false), - ExitIsSetup(false) { } + StackStateOfBB() = default; StackStateOfBB(int EntryVal, int ExitVal, bool EntrySetup, bool ExitSetup) : EntryValue(EntryVal), ExitValue(ExitVal), EntryIsSetup(EntrySetup), - ExitIsSetup(ExitSetup) { } + ExitIsSetup(ExitSetup) {} + // Can be negative, which means we are setting up a frame. - int EntryValue; - int ExitValue; - bool EntryIsSetup; - bool ExitIsSetup; + int EntryValue = 0; + int ExitValue = 0; + bool EntryIsSetup = false; + bool ExitIsSetup = false; }; -} + +} // end anonymous namespace /// Make sure on every path through the CFG, a FrameSetup is always followed /// by a FrameDestroy , stack adjustments are identical on all @@ -2090,8 +2120,8 @@ void MachineVerifier::verifyStackFrame() { df_iterator_default_set Reachable; // Visit the MBBs in DFS order. - for (df_ext_iterator > + for (df_ext_iterator> DFI = df_ext_begin(MF, Reachable), DFE = df_ext_end(MF, Reachable); DFI != DFE; ++DFI) { const MachineBasicBlock *MBB = *DFI; diff --git a/lib/CodeGen/OptimizePHIs.cpp b/lib/CodeGen/OptimizePHIs.cpp index f7aeb4204c5..6430e54a59c 100644 --- a/lib/CodeGen/OptimizePHIs.cpp +++ b/lib/CodeGen/OptimizePHIs.cpp @@ -1,4 +1,4 @@ -//===-- OptimizePHIs.cpp - Optimize machine instruction PHIs --------------===// +//===- OptimizePHIs.cpp - Optimize machine instruction PHIs ---------------===// // // The LLVM Compiler Infrastructure // @@ -14,13 +14,18 @@ #include "llvm/ADT/SmallPtrSet.h" #include "llvm/ADT/Statistic.h" +#include "llvm/CodeGen/MachineBasicBlock.h" +#include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineInstr.h" +#include "llvm/CodeGen/MachineOperand.h" #include "llvm/CodeGen/MachineRegisterInfo.h" -#include "llvm/CodeGen/Passes.h" -#include "llvm/IR/Function.h" +#include "llvm/Pass.h" #include "llvm/Target/TargetInstrInfo.h" +#include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Target/TargetSubtargetInfo.h" +#include + using namespace llvm; #define DEBUG_TYPE "opt-phis" @@ -29,12 +34,14 @@ STATISTIC(NumPHICycles, "Number of PHI cycles replaced"); STATISTIC(NumDeadPHICycles, "Number of dead PHI cycles"); namespace { + class OptimizePHIs : public MachineFunctionPass { MachineRegisterInfo *MRI; const TargetInstrInfo *TII; public: static char ID; // Pass identification + OptimizePHIs() : MachineFunctionPass(ID) { initializeOptimizePHIsPass(*PassRegistry::getPassRegistry()); } @@ -47,18 +54,21 @@ namespace { } private: - typedef SmallPtrSet InstrSet; - typedef SmallPtrSetIterator InstrSetIterator; + using InstrSet = SmallPtrSet; + using InstrSetIterator = SmallPtrSetIterator; bool IsSingleValuePHICycle(MachineInstr *MI, unsigned &SingleValReg, InstrSet &PHIsInCycle); bool IsDeadPHICycle(MachineInstr *MI, InstrSet &PHIsInCycle); bool OptimizeBB(MachineBasicBlock &MBB); }; -} + +} // end anonymous namespace char OptimizePHIs::ID = 0; + char &llvm::OptimizePHIsID = OptimizePHIs::ID; + INITIALIZE_PASS(OptimizePHIs, DEBUG_TYPE, "Optimize machine instruction PHIs", false, false) diff --git a/lib/CodeGen/PHIElimination.cpp b/lib/CodeGen/PHIElimination.cpp index 9c898fa40d7..c7f0329b3c5 100644 --- a/lib/CodeGen/PHIElimination.cpp +++ b/lib/CodeGen/PHIElimination.cpp @@ -1,4 +1,4 @@ -//===-- PhiElimination.cpp - Eliminate PHI nodes by inserting copies ------===// +//===- PhiElimination.cpp - Eliminate PHI nodes by inserting copies -------===// // // The LLVM Compiler Infrastructure // @@ -14,24 +14,35 @@ //===----------------------------------------------------------------------===// #include "PHIEliminationUtils.h" -#include "llvm/ADT/STLExtras.h" +#include "llvm/ADT/DenseMap.h" #include "llvm/ADT/SmallPtrSet.h" #include "llvm/ADT/Statistic.h" +#include "llvm/Analysis/LoopInfo.h" +#include "llvm/CodeGen/LiveInterval.h" #include "llvm/CodeGen/LiveIntervalAnalysis.h" #include "llvm/CodeGen/LiveVariables.h" +#include "llvm/CodeGen/MachineBasicBlock.h" #include "llvm/CodeGen/MachineDominators.h" +#include "llvm/CodeGen/MachineFunction.h" +#include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineInstr.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineLoopInfo.h" +#include "llvm/CodeGen/MachineOperand.h" #include "llvm/CodeGen/MachineRegisterInfo.h" -#include "llvm/CodeGen/Passes.h" -#include "llvm/IR/Function.h" +#include "llvm/CodeGen/SlotIndexes.h" +#include "llvm/Pass.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/Debug.h" #include "llvm/Support/raw_ostream.h" #include "llvm/Target/TargetInstrInfo.h" +#include "llvm/Target/TargetOpcodes.h" +#include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Target/TargetSubtargetInfo.h" -#include +#include +#include +#include + using namespace llvm; #define DEBUG_TYPE "phi-node-elimination" @@ -51,6 +62,7 @@ static cl::opt NoPhiElimLiveOutEarlyExit( cl::desc("Do not use an early exit if isLiveOutPastPHIs returns true.")); namespace { + class PHIElimination : public MachineFunctionPass { MachineRegisterInfo *MRI; // Machine register information LiveVariables *LV; @@ -58,6 +70,7 @@ namespace { public: static char ID; // Pass identification, replacement for typeid + PHIElimination() : MachineFunctionPass(ID) { initializePHIEliminationPass(*PassRegistry::getPassRegistry()); } @@ -68,8 +81,8 @@ namespace { private: /// EliminatePHINodes - Eliminate phi nodes by inserting copy instructions /// in predecessor basic blocks. - /// bool EliminatePHINodes(MachineFunction &MF, MachineBasicBlock &MBB); + void LowerPHINode(MachineBasicBlock &MBB, MachineBasicBlock::iterator LastPHIIt); @@ -78,7 +91,6 @@ namespace { /// register which is used in a PHI node. We map that to the BB the /// vreg is coming from. This is used later to determine when the vreg /// is killed in the BB. - /// void analyzePHINodes(const MachineFunction& Fn); /// Split critical edges where necessary for good coalescer performance. @@ -90,8 +102,8 @@ namespace { bool isLiveIn(unsigned Reg, const MachineBasicBlock *MBB); bool isLiveOutPastPHIs(unsigned Reg, const MachineBasicBlock *MBB); - typedef std::pair BBVRegPair; - typedef DenseMap VRegPHIUse; + using BBVRegPair = std::pair; + using VRegPHIUse = DenseMap; VRegPHIUse VRegPHIUseCount; @@ -99,17 +111,19 @@ namespace { SmallPtrSet ImpDefs; // Map reusable lowered PHI node -> incoming join register. - typedef DenseMap LoweredPHIMap; + using LoweredPHIMap = + DenseMap; LoweredPHIMap LoweredPHIs; }; -} + +} // end anonymous namespace STATISTIC(NumLowered, "Number of phis lowered"); STATISTIC(NumCriticalEdgesSplit, "Number of critical edges split"); STATISTIC(NumReused, "Number of reused lowered phis"); char PHIElimination::ID = 0; + char& llvm::PHIEliminationID = PHIElimination::ID; INITIALIZE_PASS_BEGIN(PHIElimination, DEBUG_TYPE, @@ -182,7 +196,6 @@ bool PHIElimination::runOnMachineFunction(MachineFunction &MF) { /// EliminatePHINodes - Eliminate phi nodes by inserting copy instructions in /// predecessor basic blocks. -/// bool PHIElimination::EliminatePHINodes(MachineFunction &MF, MachineBasicBlock &MBB) { if (MBB.empty() || !MBB.front().isPHI()) @@ -219,9 +232,7 @@ static bool isSourceDefinedByImplicitDef(const MachineInstr *MPhi, return true; } - -/// LowerPHINode - Lower the PHI node at the top of the specified block, -/// +/// LowerPHINode - Lower the PHI node at the top of the specified block. void PHIElimination::LowerPHINode(MachineBasicBlock &MBB, MachineBasicBlock::iterator LastPHIIt) { ++NumLowered; @@ -534,7 +545,6 @@ void PHIElimination::LowerPHINode(MachineBasicBlock &MBB, /// particular, we want to map the number of uses of a virtual register which is /// used in a PHI node. We map that to the BB the vreg is coming from. This is /// used later to determine when the vreg is killed in the BB. -/// void PHIElimination::analyzePHINodes(const MachineFunction& MF) { for (const auto &MBB : MF) for (const auto &BBI : MBB) { diff --git a/lib/CodeGen/PeepholeOptimizer.cpp b/lib/CodeGen/PeepholeOptimizer.cpp index b13f6b68c42..7cff85a3ab0 100644 --- a/lib/CodeGen/PeepholeOptimizer.cpp +++ b/lib/CodeGen/PeepholeOptimizer.cpp @@ -1,4 +1,4 @@ -//===-- PeepholeOptimizer.cpp - Peephole Optimizations --------------------===// +//===- PeepholeOptimizer.cpp - Peephole Optimizations ---------------------===// // // The LLVM Compiler Infrastructure // @@ -67,6 +67,7 @@ //===----------------------------------------------------------------------===// #include "llvm/ADT/DenseMap.h" +#include "llvm/ADT/Optional.h" #include "llvm/ADT/SmallPtrSet.h" #include "llvm/ADT/SmallSet.h" #include "llvm/ADT/SmallVector.h" @@ -74,18 +75,21 @@ #include "llvm/CodeGen/MachineBasicBlock.h" #include "llvm/CodeGen/MachineDominators.h" #include "llvm/CodeGen/MachineFunction.h" +#include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineInstr.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineLoopInfo.h" #include "llvm/CodeGen/MachineOperand.h" #include "llvm/CodeGen/MachineRegisterInfo.h" -#include "llvm/CodeGen/Passes.h" +#include "llvm/MC/LaneBitmask.h" #include "llvm/MC/MCInstrDesc.h" +#include "llvm/Pass.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/Debug.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/raw_ostream.h" #include "llvm/Target/TargetInstrInfo.h" +#include "llvm/Target/TargetOpcodes.h" #include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Target/TargetSubtargetInfo.h" #include @@ -170,11 +174,11 @@ namespace { } /// \brief Track Def -> Use info used for rewriting copies. - typedef SmallDenseMap - RewriteMapTy; + using RewriteMapTy = + SmallDenseMap; /// \brief Sequence of instructions that formulate recurrence cycle. - typedef SmallVector RecurrenceCycle; + using RecurrenceCycle = SmallVector; private: bool optimizeCmpInstr(MachineInstr *MI, MachineBasicBlock *MBB); @@ -195,6 +199,7 @@ namespace { bool foldImmediate(MachineInstr *MI, MachineBasicBlock *MBB, SmallSet &ImmDefRegs, DenseMap &ImmDefMIs); + /// \brief Finds recurrence cycles, but only ones that formulated around /// a def operand and a use operand that are tied. If there is a use /// operand commutable with the tied use operand, find recurrence cycle @@ -254,7 +259,7 @@ namespace { /// maintained with CommutePair. class RecurrenceInstr { public: - typedef std::pair IndexPair; + using IndexPair = std::pair; RecurrenceInstr(MachineInstr *MI) : MI(MI) {} RecurrenceInstr(MachineInstr *MI, unsigned Idx1, unsigned Idx2) @@ -277,11 +282,12 @@ namespace { SmallVector RegSrcs; /// Instruction using the sources in 'RegSrcs'. - const MachineInstr *Inst; + const MachineInstr *Inst = nullptr; public: - ValueTrackerResult() : Inst(nullptr) {} - ValueTrackerResult(unsigned Reg, unsigned SubReg) : Inst(nullptr) { + ValueTrackerResult() = default; + + ValueTrackerResult(unsigned Reg, unsigned SubReg) { addSource(Reg, SubReg); } @@ -350,13 +356,17 @@ namespace { class ValueTracker { private: /// The current point into the use-def chain. - const MachineInstr *Def; + const MachineInstr *Def = nullptr; + /// The index of the definition in Def. - unsigned DefIdx; + unsigned DefIdx = 0; + /// The sub register index of the definition. unsigned DefSubReg; + /// The register where the value can be found. unsigned Reg; + /// Specifiy whether or not the value tracking looks through /// complex instructions. When this is false, the value tracker /// bails on everything that is not a copy or a bitcast. @@ -365,8 +375,10 @@ namespace { /// the ValueTracker class but that would have complicated the code of /// the users of this class. bool UseAdvancedTracking; + /// MachineRegisterInfo used to perform tracking. const MachineRegisterInfo &MRI; + /// Optional TargetInstrInfo used to perform some complex /// tracking. const TargetInstrInfo *TII; @@ -374,22 +386,29 @@ namespace { /// \brief Dispatcher to the right underlying implementation of /// getNextSource. ValueTrackerResult getNextSourceImpl(); + /// \brief Specialized version of getNextSource for Copy instructions. ValueTrackerResult getNextSourceFromCopy(); + /// \brief Specialized version of getNextSource for Bitcast instructions. ValueTrackerResult getNextSourceFromBitcast(); + /// \brief Specialized version of getNextSource for RegSequence /// instructions. ValueTrackerResult getNextSourceFromRegSequence(); + /// \brief Specialized version of getNextSource for InsertSubreg /// instructions. ValueTrackerResult getNextSourceFromInsertSubreg(); + /// \brief Specialized version of getNextSource for ExtractSubreg /// instructions. ValueTrackerResult getNextSourceFromExtractSubreg(); + /// \brief Specialized version of getNextSource for SubregToReg /// instructions. ValueTrackerResult getNextSourceFromSubregToReg(); + /// \brief Specialized version of getNextSource for PHI instructions. ValueTrackerResult getNextSourceFromPHI(); @@ -410,7 +429,7 @@ namespace { const MachineRegisterInfo &MRI, bool UseAdvancedTracking = false, const TargetInstrInfo *TII = nullptr) - : Def(nullptr), DefIdx(0), DefSubReg(DefSubReg), Reg(Reg), + : DefSubReg(DefSubReg), Reg(Reg), UseAdvancedTracking(UseAdvancedTracking), MRI(MRI), TII(TII) { if (!TargetRegisterInfo::isPhysicalRegister(Reg)) { Def = MRI.getVRegDef(Reg); @@ -453,6 +472,7 @@ namespace { } // end anonymous namespace char PeepholeOptimizer::ID = 0; + char &llvm::PeepholeOptimizerID = PeepholeOptimizer::ID; INITIALIZE_PASS_BEGIN(PeepholeOptimizer, DEBUG_TYPE, @@ -659,7 +679,7 @@ bool PeepholeOptimizer::optimizeSelect(MachineInstr *MI, } /// \brief Check if a simpler conditional branch can be -// generated +/// generated bool PeepholeOptimizer::optimizeCondBranch(MachineInstr *MI) { return TII->optimizeCondBranch(*MI); } @@ -805,13 +825,13 @@ class CopyRewriter { protected: /// The copy-like instruction. MachineInstr &CopyLike; + /// The index of the source being rewritten. - unsigned CurrentSrcIdx; + unsigned CurrentSrcIdx = 0; public: - CopyRewriter(MachineInstr &MI) : CopyLike(MI), CurrentSrcIdx(0) {} - - virtual ~CopyRewriter() {} + CopyRewriter(MachineInstr &MI) : CopyLike(MI) {} + virtual ~CopyRewriter() = default; /// \brief Get the next rewritable source (SrcReg, SrcSubReg) and /// the related value that it affects (TrackReg, TrackSubReg). @@ -944,6 +964,7 @@ class UncoalescableRewriter : public CopyRewriter { protected: const TargetInstrInfo &TII; MachineRegisterInfo &MRI; + /// The number of defs in the bitcast unsigned NumDefs; @@ -958,7 +979,6 @@ public: /// All such sources need to be considered rewritable in order to /// rewrite a uncoalescable copy-like instruction. This method return /// each definition that must be checked if rewritable. - /// bool getNextRewritableSource(unsigned &SrcReg, unsigned &SrcSubReg, unsigned &TrackReg, unsigned &TrackSubReg) override { @@ -1205,7 +1225,7 @@ public: } }; -} // end anonymous namespace +} // end anonymous namespace /// \brief Get the appropriated CopyRewriter for \p MI. /// \return A pointer to a dynamically allocated CopyRewriter or nullptr @@ -1847,7 +1867,6 @@ bool PeepholeOptimizer::runOnMachineFunction(MachineFunction &MF) { DEBUG(dbgs() << "Encountered load fold barrier on " << *MI << "\n"); FoldAsLoadDefCandidates.clear(); } - } } -- 2.50.1