From 8d6095aa06175e68324bd8b91b62c348dd897cb0 Mon Sep 17 00:00:00 2001 From: Sander de Smalen Date: Fri, 20 Jul 2018 08:47:26 +0000 Subject: [PATCH] [AArch64][SVE] Asm: Support for FTMAD instruction. Floating-point trigonometric multiply-add coefficient, e.g. ftmad z0.h, z0.h, z1.h, #7 with variants for 16, 32 and 64-bit elements. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337533 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/AArch64/AArch64SVEInstrInfo.td | 2 ++ lib/Target/AArch64/SVEInstrFormats.td | 25 +++++++++++++++ test/MC/AArch64/SVE/ftmad-diagnostics.s | 38 +++++++++++++++++++++++ test/MC/AArch64/SVE/ftmad.s | 26 ++++++++++++++++ 4 files changed, 91 insertions(+) create mode 100644 test/MC/AArch64/SVE/ftmad-diagnostics.s create mode 100644 test/MC/AArch64/SVE/ftmad.s diff --git a/lib/Target/AArch64/AArch64SVEInstrInfo.td b/lib/Target/AArch64/AArch64SVEInstrInfo.td index a5569d2ad61..028cb3bc9f6 100644 --- a/lib/Target/AArch64/AArch64SVEInstrInfo.td +++ b/lib/Target/AArch64/AArch64SVEInstrInfo.td @@ -145,6 +145,8 @@ let Predicates = [HasSVE] in { defm FNMAD_ZPmZZ : sve_fp_3op_p_zds_b<0b10, "fnmad">; defm FNMSB_ZPmZZ : sve_fp_3op_p_zds_b<0b11, "fnmsb">; + defm FTMAD_ZZI : sve_fp_ftmad<"ftmad">; + defm FMLA_ZZZI : sve_fp_fma_by_indexed_elem<0b0, "fmla">; defm FMLS_ZZZI : sve_fp_fma_by_indexed_elem<0b1, "fmls">; diff --git a/lib/Target/AArch64/SVEInstrFormats.td b/lib/Target/AArch64/SVEInstrFormats.td index 642e48f3063..e90e30940d9 100644 --- a/lib/Target/AArch64/SVEInstrFormats.td +++ b/lib/Target/AArch64/SVEInstrFormats.td @@ -985,6 +985,31 @@ multiclass sve_fp_2op_p_zds opc, string asm> { def _D : sve_fp_2op_p_zds<0b11, opc, asm, ZPR64>; } +class sve_fp_ftmad sz, string asm, ZPRRegOp zprty> +: I<(outs zprty:$Zdn), (ins zprty:$_Zdn, zprty:$Zm, imm0_7:$imm3), + asm, "\t$Zdn, $_Zdn, $Zm, $imm3", + "", + []>, Sched<[]> { + bits<5> Zdn; + bits<5> Zm; + bits<3> imm3; + let Inst{31-24} = 0b01100101; + let Inst{23-22} = sz; + let Inst{21-19} = 0b010; + let Inst{18-16} = imm3; + let Inst{15-10} = 0b100000; + let Inst{9-5} = Zm; + let Inst{4-0} = Zdn; + + let Constraints = "$Zdn = $_Zdn"; +} + +multiclass sve_fp_ftmad { + def _H : sve_fp_ftmad<0b01, asm, ZPR16>; + def _S : sve_fp_ftmad<0b10, asm, ZPR32>; + def _D : sve_fp_ftmad<0b11, asm, ZPR64>; +} + //===----------------------------------------------------------------------===// // SVE Floating Point Arithmetic - Unpredicated Group diff --git a/test/MC/AArch64/SVE/ftmad-diagnostics.s b/test/MC/AArch64/SVE/ftmad-diagnostics.s new file mode 100644 index 00000000000..5b63106fb48 --- /dev/null +++ b/test/MC/AArch64/SVE/ftmad-diagnostics.s @@ -0,0 +1,38 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Invalid element size + +ftmad z0.b, z0.b, z1.b, #7 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: ftmad z0.b, z0.b, z1.b, #7 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ftmad z0.b, z0.b, z1.h, #7 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: ftmad z0.b, z0.b, z1.h, #7 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// ------------------------------------------------------------------------- // +// Tied operands must match + +ftmad z0.h, z1.h, z2.h, #7 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register +// CHECK-NEXT: ftmad z0.h, z1.h, z2.h, #7 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// ------------------------------------------------------------------------- // +// Invalid immediate range + +ftmad z0.h, z0.h, z1.h, #-1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7]. +// CHECK-NEXT: ftmad z0.h, z0.h, z1.h, #-1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ftmad z0.h, z0.h, z1.h, #8 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7]. +// CHECK-NEXT: ftmad z0.h, z0.h, z1.h, #8 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/ftmad.s b/test/MC/AArch64/SVE/ftmad.s new file mode 100644 index 00000000000..c18009ec0cb --- /dev/null +++ b/test/MC/AArch64/SVE/ftmad.s @@ -0,0 +1,26 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +ftmad z0.h, z0.h, z31.h, #7 +// CHECK-INST: ftmad z0.h, z0.h, z31.h, #7 +// CHECK-ENCODING: [0xe0,0x83,0x57,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 83 57 65 + +ftmad z0.s, z0.s, z31.s, #7 +// CHECK-INST: ftmad z0.s, z0.s, z31.s, #7 +// CHECK-ENCODING: [0xe0,0x83,0x97,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 83 97 65 + +ftmad z0.d, z0.d, z31.d, #7 +// CHECK-INST: ftmad z0.d, z0.d, z31.d, #7 +// CHECK-ENCODING: [0xe0,0x83,0xd7,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 83 d7 65 -- 2.50.1