From 8aa95af9e5c229e240133016a91e6b09341ca473 Mon Sep 17 00:00:00 2001
From: Matthias Braun <matze@braunis.de>
Date: Thu, 26 Jul 2018 17:43:56 +0000
Subject: [PATCH] MacroFusion: Fix macro fusion with ExitSU failing in top-down
 scheduling

When fusing instructions A and B, we must add all predecessors of B as
predecessors of A to avoid instructions getting scheduling in between.

There is a special case involving ExitSU: Every other node must be
scheduled before it by design and we don't need to make this explicit in
the graph, however when fusing with a different node we need to schedule
every othere node before the fused node too and we need to make this
explicit now: This patch adds a dependency from the fused node to all
roots in the graph.

Differential Revision: https://reviews.llvm.org/D49830

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338046 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/CodeGen/MacroFusion.cpp                | 12 +++++++++-
 test/CodeGen/AArch64/macro-fusion-last.mir | 28 ++++++++++++++++++++++
 2 files changed, 39 insertions(+), 1 deletion(-)
 create mode 100644 test/CodeGen/AArch64/macro-fusion-last.mir

diff --git a/lib/CodeGen/MacroFusion.cpp b/lib/CodeGen/MacroFusion.cpp
index 2df72d83aaf..62dadbba0c1 100644
--- a/lib/CodeGen/MacroFusion.cpp
+++ b/lib/CodeGen/MacroFusion.cpp
@@ -87,7 +87,7 @@ static bool fuseInstructionPair(ScheduleDAGMI &DAG, SUnit &FirstSU,
 
   // Make the FirstSU also dependent on the dependencies of the SecondSU to
   // prevent them from being scheduled between the FirstSU and the SecondSU.
-  if (&FirstSU != &DAG.EntrySU)
+  if (&FirstSU != &DAG.EntrySU) {
     for (const SDep &SI : SecondSU.Preds) {
       SUnit *SU = SI.getSUnit();
       if (SI.isWeak() || isHazard(SI) || &FirstSU == SU || FirstSU.isSucc(SU))
@@ -96,6 +96,16 @@ static bool fuseInstructionPair(ScheduleDAGMI &DAG, SUnit &FirstSU,
                  FirstSU.print(dbgs(), &DAG); dbgs() << '\n';);
       DAG.addEdge(&FirstSU, SDep(SU, SDep::Artificial));
     }
+    // ExitSU comes last by design, which acts like an implicit dependency
+    // between ExitSU and any bottom root in the graph. We should transfer
+    // this to FirstSU as well.
+    if (&SecondSU == &DAG.ExitSU) {
+      for (SUnit &SU : DAG.SUnits) {
+        if (SU.Succs.empty())
+          DAG.addEdge(&FirstSU, SDep(&SU, SDep::Artificial));
+      }
+    }
+  }
 
   ++NumFused;
   return true;
diff --git a/test/CodeGen/AArch64/macro-fusion-last.mir b/test/CodeGen/AArch64/macro-fusion-last.mir
new file mode 100644
index 00000000000..14937a4794e
--- /dev/null
+++ b/test/CodeGen/AArch64/macro-fusion-last.mir
@@ -0,0 +1,28 @@
+# RUN: llc -o - %s -mtriple=aarch64-- -mattr=+arith-bcc-fusion -run-pass postmisched | FileCheck %s --check-prefixes=CHECK,FUSION
+# RUN: llc -o - %s -mtriple=aarch64-- -mattr=-arith-bcc-fusion -run-pass postmisched | FileCheck %s --check-prefixes=CHECK,NOFUSION
+# Make sure the last instruction is correctly macro-fused when scheduling
+# top-down (post-ra).
+---
+# CHECK-LABEL: name: fuse_last
+# CHECK: $x1 = LDRXui $x0, 0
+# NOFUSION: $xzr = SUBSXri killed $x2, 0, 0, implicit-def $nzcv
+# CHECK: STRXui killed $x0, killed $x1, 0
+# FUSION: $xzr = SUBSXri killed $x2, 0, 0, implicit-def $nzcv
+# CHECK: Bcc 1, %bb.1, implicit killed $nzcv
+name: fuse_last
+tracksRegLiveness: true
+body: |
+  bb.0:
+    liveins: $x0, $x2
+
+    $x1 = LDRXui $x0, 0
+    ; There is latency between these two instructions tempting the scheduler to
+    ; move the SUBSXri in between them. However doing so breaks macro fusion.
+    STRXui $x0, $x1, 0
+
+    $xzr = SUBSXri $x2, 0, 0, implicit-def $nzcv
+    Bcc 1, %bb.1, implicit killed $nzcv
+
+  bb.1:
+    RET_ReallyLR implicit undef $x0
+...
-- 
2.50.1