From 8a9af26e2832b206c7660c00d0bb802ad8f12162 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Fri, 15 Jul 2016 21:26:46 +0000 Subject: [PATCH] AMDGPU/R600: Delete dead code. Dead or the same as the base implementation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275616 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/AMDGPU/R600InstrInfo.cpp | 44 +---------------------------- lib/Target/AMDGPU/R600InstrInfo.h | 15 ---------- 2 files changed, 1 insertion(+), 58 deletions(-) diff --git a/lib/Target/AMDGPU/R600InstrInfo.cpp b/lib/Target/AMDGPU/R600InstrInfo.cpp index 8e4553d257a..1c5f7ec1b6e 100644 --- a/lib/Target/AMDGPU/R600InstrInfo.cpp +++ b/lib/Target/AMDGPU/R600InstrInfo.cpp @@ -31,10 +31,6 @@ using namespace llvm; R600InstrInfo::R600InstrInfo(const R600Subtarget &ST) : AMDGPUInstrInfo(ST), RI(), ST(ST) {} -bool R600InstrInfo::isTrig(const MachineInstr &MI) const { - return get(MI.getOpcode()).TSFlags & R600_InstFlag::TRIG; -} - bool R600InstrInfo::isVector(const MachineInstr &MI) const { return get(MI.getOpcode()).TSFlags & R600_InstFlag::VECTOR; } @@ -96,17 +92,6 @@ bool R600InstrInfo::isMov(unsigned Opcode) const { } } -// Some instructions act as place holders to emulate operations that the GPU -// hardware does automatically. This function can be used to check if -// an opcode falls into this category. -bool R600InstrInfo::isPlaceHolderOpcode(unsigned Opcode) const { - switch (Opcode) { - default: return false; - case AMDGPU::RETURN: - return true; - } -} - bool R600InstrInfo::isReductionOp(unsigned Opcode) const { return false; } @@ -144,10 +129,6 @@ bool R600InstrInfo::isLDSInstr(unsigned Opcode) const { (TargetFlags & R600_InstFlag::LDS_1A2D)); } -bool R600InstrInfo::isLDSNoRetInstr(unsigned Opcode) const { - return isLDSInstr(Opcode) && getOperandIdx(Opcode, AMDGPU::OpName::dst) == -1; -} - bool R600InstrInfo::isLDSRetInstr(unsigned Opcode) const { return isLDSInstr(Opcode) && getOperandIdx(Opcode, AMDGPU::OpName::dst) != -1; } @@ -248,17 +229,6 @@ bool R600InstrInfo::readsLDSSrcReg(const MachineInstr &MI) const { return false; } -int R600InstrInfo::getSrcIdx(unsigned Opcode, unsigned SrcNum) const { - static const unsigned OpTable[] = { - AMDGPU::OpName::src0, - AMDGPU::OpName::src1, - AMDGPU::OpName::src2 - }; - - assert (SrcNum < 3); - return getOperandIdx(Opcode, OpTable[SrcNum]); -} - int R600InstrInfo::getSelIdx(unsigned Opcode, unsigned SrcIdx) const { static const unsigned SrcSelTable[][2] = { {AMDGPU::OpName::src0, AMDGPU::OpName::src0_sel}, @@ -407,8 +377,7 @@ Swizzle(std::vector > Src, return Src; } -static unsigned -getTransSwizzle(R600InstrInfo::BankSwizzle Swz, unsigned Op) { +static unsigned getTransSwizzle(R600InstrInfo::BankSwizzle Swz, unsigned Op) { switch (Swz) { case R600InstrInfo::ALU_VEC_012_SCL_210: { unsigned Cycles[3] = { 2, 1, 0}; @@ -428,7 +397,6 @@ getTransSwizzle(R600InstrInfo::BankSwizzle Swz, unsigned Op) { } default: llvm_unreachable("Wrong Swizzle for Trans Slot"); - return 0; } } @@ -981,12 +949,6 @@ bool R600InstrInfo::DefinesPredicate(MachineInstr &MI, } -bool -R600InstrInfo::SubsumesPredicate(ArrayRef Pred1, - ArrayRef Pred2) const { - return false; -} - bool R600InstrInfo::PredicateInstruction(MachineInstr &MI, ArrayRef Pred) const { int PIdx = MI.findFirstPredOperandIdx(); @@ -1420,10 +1382,6 @@ void R600InstrInfo::setImmOperand(MachineInstr &MI, unsigned Op, // Instruction flag getters/setters //===----------------------------------------------------------------------===// -bool R600InstrInfo::hasFlagOperand(const MachineInstr &MI) const { - return GET_FLAG_OPERAND_IDX(get(MI.getOpcode()).TSFlags) != 0; -} - MachineOperand &R600InstrInfo::getFlagOp(MachineInstr &MI, unsigned SrcIdx, unsigned Flag) const { unsigned TargetFlags = get(MI.getOpcode()).TSFlags; diff --git a/lib/Target/AMDGPU/R600InstrInfo.h b/lib/Target/AMDGPU/R600InstrInfo.h index a9d583703e6..feaca98def4 100644 --- a/lib/Target/AMDGPU/R600InstrInfo.h +++ b/lib/Target/AMDGPU/R600InstrInfo.h @@ -68,8 +68,6 @@ public: bool isLegalToSplitMBBAt(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const override; - bool isTrig(const MachineInstr &MI) const; - bool isPlaceHolderOpcode(unsigned opcode) const; bool isReductionOp(unsigned opcode) const; bool isCubeOp(unsigned opcode) const; @@ -77,7 +75,6 @@ public: bool isALUInstr(unsigned Opcode) const; bool hasInstrModifiers(unsigned Opcode) const; bool isLDSInstr(unsigned Opcode) const; - bool isLDSNoRetInstr(unsigned Opcode) const; bool isLDSRetInstr(unsigned Opcode) const; /// \returns true if this \p Opcode represents an ALU instruction or an @@ -100,9 +97,6 @@ public: bool definesAddressRegister(MachineInstr &MI) const; bool readsLDSSrcReg(const MachineInstr &MI) const; - /// \returns The operand index for the given source number. Legal values - /// for SrcNum are 0, 1, and 2. - int getSrcIdx(unsigned Opcode, unsigned SrcNum) const; /// \returns The operand Index for the Sel operand given an index to one /// of the instruction's src operands. int getSelIdx(unsigned Opcode, unsigned SrcIdx) const; @@ -191,9 +185,6 @@ public: bool DefinesPredicate(MachineInstr &MI, std::vector &Pred) const override; - bool SubsumesPredicate(ArrayRef Pred1, - ArrayRef Pred2) const override; - bool isProfitableToUnpredicate(MachineBasicBlock &TMBB, MachineBasicBlock &FMBB) const override; @@ -206,9 +197,6 @@ public: const MachineInstr &MI, unsigned *PredCost = nullptr) const override; - int getInstrLatency(const InstrItineraryData *ItinData, - SDNode *Node) const override { return 1;} - bool expandPostRAPseudo(MachineInstr &MI) const override; /// \brief Reserve the registers that may be accesed using indirect addressing. @@ -296,9 +284,6 @@ public: /// \brief Helper function for setting instruction flag values. void setImmOperand(MachineInstr &MI, unsigned Op, int64_t Imm) const; - /// \returns true if this instruction has an operand for storing target flags. - bool hasFlagOperand(const MachineInstr &MI) const; - ///\brief Add one of the MO_FLAG* flags to the specified \p Operand. void addFlag(MachineInstr &MI, unsigned Operand, unsigned Flag) const; -- 2.49.0