From 8a67530447904892b22a0a90588e3359a956e69b Mon Sep 17 00:00:00 2001 From: Benjamin Kramer Date: Fri, 23 Aug 2019 19:59:23 +0000 Subject: [PATCH] Do a sweep of symbol internalization. NFC. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@369803 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Bitcode/Writer/BitcodeWriter.cpp | 2 +- .../SelectionDAG/SelectionDAGBuilder.cpp | 5 +++-- lib/CodeGen/TargetPassConfig.cpp | 21 +++++++++++-------- lib/IR/DIBuilder.cpp | 2 +- lib/LTO/SummaryBasedOptimizations.cpp | 2 +- lib/MC/MCDwarf.cpp | 4 ++-- lib/Remarks/RemarkParser.cpp | 2 ++ lib/Support/FileCheck.cpp | 2 +- .../AArch64/AArch64SpeculationHardening.cpp | 6 +++--- .../Hexagon/HexagonLoopIdiomRecognition.cpp | 6 +++--- lib/Target/Hexagon/HexagonVLIWPacketizer.cpp | 6 +++--- .../MCTargetDesc/HexagonMCTargetDesc.cpp | 2 +- lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp | 2 +- lib/Target/RISCV/RISCVISelLowering.cpp | 4 ++-- lib/Target/X86/X86IndirectBranchTracking.cpp | 2 +- lib/Transforms/Scalar/LoopFuse.cpp | 4 ++-- 16 files changed, 39 insertions(+), 33 deletions(-) diff --git a/lib/Bitcode/Writer/BitcodeWriter.cpp b/lib/Bitcode/Writer/BitcodeWriter.cpp index 5c7b970a3a7..0eea6dc87ce 100644 --- a/lib/Bitcode/Writer/BitcodeWriter.cpp +++ b/lib/Bitcode/Writer/BitcodeWriter.cpp @@ -86,7 +86,7 @@ static cl::opt cl::desc("Number of metadatas above which we emit an index " "to enable lazy-loading")); -cl::opt WriteRelBFToSummary( +static cl::opt WriteRelBFToSummary( "write-relbf-to-summary", cl::Hidden, cl::init(false), cl::desc("Write relative block frequency to function summary ")); diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp index b899260a84e..bacc8ff82ee 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp @@ -5327,8 +5327,9 @@ static SDValue ExpandPowI(const SDLoc &DL, SDValue LHS, SDValue RHS, // getUnderlyingArgRegs - Find underlying registers used for a truncated, // bitcasted, or split argument. Returns a list of -void getUnderlyingArgRegs(SmallVectorImpl> &Regs, - const SDValue &N) { +static void +getUnderlyingArgRegs(SmallVectorImpl> &Regs, + const SDValue &N) { switch (N.getOpcode()) { case ISD::CopyFromReg: { SDValue Op = N.getOperand(1); diff --git a/lib/CodeGen/TargetPassConfig.cpp b/lib/CodeGen/TargetPassConfig.cpp index 953d307cf59..ba780e718bb 100644 --- a/lib/CodeGen/TargetPassConfig.cpp +++ b/lib/CodeGen/TargetPassConfig.cpp @@ -49,9 +49,10 @@ using namespace llvm; -cl::opt EnableIPRA("enable-ipra", cl::init(false), cl::Hidden, - cl::desc("Enable interprocedural register allocation " - "to reduce load/store at procedure calls.")); +static cl::opt + EnableIPRA("enable-ipra", cl::init(false), cl::Hidden, + cl::desc("Enable interprocedural register allocation " + "to reduce load/store at procedure calls.")); static cl::opt DisablePostRASched("disable-post-ra", cl::Hidden, cl::desc("Disable Post Regalloc Scheduler")); static cl::opt DisableBranchFold("disable-branch-fold", cl::Hidden, @@ -152,8 +153,10 @@ static cl::opt EnableGlobalISelAbort( // substitutePass(&PostRASchedulerID, &PostMachineSchedulerID). // Targets can return true in targetSchedulesPostRAScheduling() and // insert a PostRA scheduling pass wherever it wants. -cl::opt MISchedPostRA("misched-postra", cl::Hidden, - cl::desc("Run MachineScheduler post regalloc (independent of preRA sched)")); +static cl::opt MISchedPostRA( + "misched-postra", cl::Hidden, + cl::desc( + "Run MachineScheduler post regalloc (independent of preRA sched)")); // Experimental option to run live interval analysis early. static cl::opt EarlyLiveIntervals("early-live-intervals", cl::Hidden, @@ -175,10 +178,10 @@ static cl::opt UseCFLAA( /// Option names for limiting the codegen pipeline. /// Those are used in error reporting and we didn't want /// to duplicate their names all over the place. -const char *StartAfterOptName = "start-after"; -const char *StartBeforeOptName = "start-before"; -const char *StopAfterOptName = "stop-after"; -const char *StopBeforeOptName = "stop-before"; +static const char *StartAfterOptName = "start-after"; +static const char *StartBeforeOptName = "start-before"; +static const char *StopAfterOptName = "stop-after"; +static const char *StopBeforeOptName = "stop-before"; static cl::opt StartAfterOpt(StringRef(StartAfterOptName), diff --git a/lib/IR/DIBuilder.cpp b/lib/IR/DIBuilder.cpp index 2493c6cbe53..5d567122743 100644 --- a/lib/IR/DIBuilder.cpp +++ b/lib/IR/DIBuilder.cpp @@ -25,7 +25,7 @@ using namespace llvm; using namespace llvm::dwarf; -cl::opt +static cl::opt UseDbgAddr("use-dbg-addr", llvm::cl::desc("Use llvm.dbg.addr for all local variables"), cl::init(false), cl::Hidden); diff --git a/lib/LTO/SummaryBasedOptimizations.cpp b/lib/LTO/SummaryBasedOptimizations.cpp index e919fd530fb..6db495de003 100644 --- a/lib/LTO/SummaryBasedOptimizations.cpp +++ b/lib/LTO/SummaryBasedOptimizations.cpp @@ -18,7 +18,7 @@ using namespace llvm; -cl::opt ThinLTOSynthesizeEntryCounts( +static cl::opt ThinLTOSynthesizeEntryCounts( "thinlto-synthesize-entry-counts", cl::init(false), cl::Hidden, cl::desc("Synthesize entry counts based on the summary")); diff --git a/lib/MC/MCDwarf.cpp b/lib/MC/MCDwarf.cpp index 8456b3421bc..bcc7c45afc0 100644 --- a/lib/MC/MCDwarf.cpp +++ b/lib/MC/MCDwarf.cpp @@ -544,8 +544,8 @@ Expected MCDwarfLineTable::tryGetFile(StringRef &Directory, FileNumber); } -bool isRootFile(const MCDwarfFile &RootFile, StringRef &Directory, - StringRef &FileName, Optional Checksum) { +static bool isRootFile(const MCDwarfFile &RootFile, StringRef &Directory, + StringRef &FileName, Optional Checksum) { if (RootFile.Name.empty() || RootFile.Name != FileName.data()) return false; return RootFile.Checksum == Checksum; diff --git a/lib/Remarks/RemarkParser.cpp b/lib/Remarks/RemarkParser.cpp index 5c441ca343f..98f65349065 100644 --- a/lib/Remarks/RemarkParser.cpp +++ b/lib/Remarks/RemarkParser.cpp @@ -105,6 +105,7 @@ llvm::remarks::createRemarkParserFromMeta(Format ParserFormat, StringRef Buf, llvm_unreachable("unhandled ParseFormat"); } +namespace { // Wrapper that holds the state needed to interact with the C API. struct CParser { std::unique_ptr TheParser; @@ -120,6 +121,7 @@ struct CParser { bool hasError() const { return Err.hasValue(); } const char *getMessage() const { return Err ? Err->c_str() : nullptr; }; }; +} // namespace // Create wrappers for C Binding types (see CBindingWrapping.h). DEFINE_SIMPLE_CONVERSION_FUNCTIONS(CParser, LLVMRemarkParserRef) diff --git a/lib/Support/FileCheck.cpp b/lib/Support/FileCheck.cpp index 143f7a46f84..9310a7911a7 100644 --- a/lib/Support/FileCheck.cpp +++ b/lib/Support/FileCheck.cpp @@ -125,7 +125,7 @@ FileCheckPattern::parseVariable(StringRef &Str, const SourceMgr &SM) { // StringRef holding all characters considered as horizontal whitespaces by // FileCheck input canonicalization. -StringRef SpaceChars = " \t"; +constexpr StringLiteral SpaceChars = " \t"; // Parsing helper function that strips the first character in S and returns it. static char popFront(StringRef &S) { diff --git a/lib/Target/AArch64/AArch64SpeculationHardening.cpp b/lib/Target/AArch64/AArch64SpeculationHardening.cpp index dcafb18c2b3..21ad8e48b1f 100644 --- a/lib/Target/AArch64/AArch64SpeculationHardening.cpp +++ b/lib/Target/AArch64/AArch64SpeculationHardening.cpp @@ -115,9 +115,9 @@ using namespace llvm; #define AARCH64_SPECULATION_HARDENING_NAME "AArch64 speculation hardening pass" -cl::opt HardenLoads("aarch64-slh-loads", cl::Hidden, - cl::desc("Sanitize loads from memory."), - cl::init(true)); +static cl::opt HardenLoads("aarch64-slh-loads", cl::Hidden, + cl::desc("Sanitize loads from memory."), + cl::init(true)); namespace { diff --git a/lib/Target/Hexagon/HexagonLoopIdiomRecognition.cpp b/lib/Target/Hexagon/HexagonLoopIdiomRecognition.cpp index ac48e1dc30b..d6e40dda02f 100644 --- a/lib/Target/Hexagon/HexagonLoopIdiomRecognition.cpp +++ b/lib/Target/Hexagon/HexagonLoopIdiomRecognition.cpp @@ -93,9 +93,9 @@ static cl::opt OnlyNonNestedMemmove("only-nonnested-memmove-idiom", cl::Hidden, cl::init(true), cl::desc("Only enable generating memmove in non-nested loops")); -cl::opt HexagonVolatileMemcpy("disable-hexagon-volatile-memcpy", - cl::Hidden, cl::init(false), - cl::desc("Enable Hexagon-specific memcpy for volatile destination.")); +static cl::opt HexagonVolatileMemcpy( + "disable-hexagon-volatile-memcpy", cl::Hidden, cl::init(false), + cl::desc("Enable Hexagon-specific memcpy for volatile destination.")); static cl::opt SimplifyLimit("hlir-simplify-limit", cl::init(10000), cl::Hidden, cl::desc("Maximum number of simplification steps in HLIR")); diff --git a/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp b/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp index e4cc8295a9f..c89c0b3369f 100644 --- a/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp +++ b/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp @@ -57,9 +57,9 @@ static cl::opt DisablePacketizer("disable-packetizer", cl::Hidden, cl::ZeroOrMore, cl::init(false), cl::desc("Disable Hexagon packetizer pass")); -cl::opt Slot1Store("slot1-store-slot0-load", cl::Hidden, - cl::ZeroOrMore, cl::init(true), - cl::desc("Allow slot1 store and slot0 load")); +static cl::opt Slot1Store("slot1-store-slot0-load", cl::Hidden, + cl::ZeroOrMore, cl::init(true), + cl::desc("Allow slot1 store and slot0 load")); static cl::opt PacketizeVolatiles("hexagon-packetize-volatiles", cl::ZeroOrMore, cl::Hidden, cl::init(true), diff --git a/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp b/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp index 9c50b25156c..7758c37d612 100644 --- a/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp +++ b/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp @@ -72,7 +72,6 @@ cl::opt MV65("mv65", cl::Hidden, cl::desc("Build for Hexagon V65"), cl::init(false)); cl::opt MV66("mv66", cl::Hidden, cl::desc("Build for Hexagon V66"), cl::init(false)); -} // namespace cl::opt EnableHVX("mhvx", @@ -86,6 +85,7 @@ cl::opt clEnumValN(Hexagon::ArchEnum::Generic, "", "")), // Sentinel for flag not present. cl::init(Hexagon::ArchEnum::NoArch), cl::ValueOptional); +} // namespace static cl::opt DisableHVX("mno-hvx", cl::Hidden, diff --git a/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp index 9605444080c..587725db7ea 100644 --- a/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp +++ b/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp @@ -744,7 +744,7 @@ public: // Return the matching FPR64 register for the given FPR32. // FIXME: Ideally this function could be removed in favour of using // information from TableGen. -Register convertFPR32ToFPR64(Register Reg) { +static Register convertFPR32ToFPR64(Register Reg) { switch (Reg) { default: llvm_unreachable("Not a recognised FPR32 register"); diff --git a/lib/Target/RISCV/RISCVISelLowering.cpp b/lib/Target/RISCV/RISCVISelLowering.cpp index 126c70eddfd..032074b89ea 100644 --- a/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/lib/Target/RISCV/RISCVISelLowering.cpp @@ -1078,8 +1078,8 @@ unsigned RISCVTargetLowering::ComputeNumSignBitsForTargetNode( return 1; } -MachineBasicBlock *emitReadCycleWidePseudo(MachineInstr &MI, - MachineBasicBlock *BB) { +static MachineBasicBlock *emitReadCycleWidePseudo(MachineInstr &MI, + MachineBasicBlock *BB) { assert(MI.getOpcode() == RISCV::ReadCycleWide && "Unexpected instruction"); // To read the 64-bit cycle CSR on a 32-bit target, we read the two halves. diff --git a/lib/Target/X86/X86IndirectBranchTracking.cpp b/lib/Target/X86/X86IndirectBranchTracking.cpp index 04e8b2231fe..cc0f59ab329 100644 --- a/lib/Target/X86/X86IndirectBranchTracking.cpp +++ b/lib/Target/X86/X86IndirectBranchTracking.cpp @@ -84,7 +84,7 @@ bool X86IndirectBranchTrackingPass::addENDBR( return false; } -bool IsCallReturnTwice(llvm::MachineOperand &MOp) { +static bool IsCallReturnTwice(llvm::MachineOperand &MOp) { if (!MOp.isGlobal()) return false; auto *CalleeFn = dyn_cast(MOp.getGlobal()); diff --git a/lib/Transforms/Scalar/LoopFuse.cpp b/lib/Transforms/Scalar/LoopFuse.cpp index 558400c24a1..704a71e1c5c 100644 --- a/lib/Transforms/Scalar/LoopFuse.cpp +++ b/lib/Transforms/Scalar/LoopFuse.cpp @@ -110,6 +110,7 @@ static cl::opt cl::Hidden, cl::init(false), cl::ZeroOrMore); #endif +namespace { /// This class is used to represent a candidate for loop fusion. When it is /// constructed, it checks the conditions for loop fusion to ensure that it /// represents a valid candidate. It caches several parts of a loop that are @@ -338,7 +339,6 @@ struct FusionCandidateCompare { } }; -namespace { using LoopVector = SmallVector; // Set of Control Flow Equivalent (CFE) Fusion Candidates, sorted in dominance @@ -353,7 +353,6 @@ using LoopVector = SmallVector; // keeps the FusionCandidateSet sorted will also simplify the implementation. using FusionCandidateSet = std::set; using FusionCandidateCollection = SmallVector; -} // namespace inline llvm::raw_ostream &operator<<(llvm::raw_ostream &OS, const FusionCandidateSet &CandSet) { @@ -1211,6 +1210,7 @@ struct LoopFuseLegacy : public FunctionPass { return LF.fuseLoops(F); } }; +} // namespace PreservedAnalyses LoopFusePass::run(Function &F, FunctionAnalysisManager &AM) { auto &LI = AM.getResult(F); -- 2.40.0