From 89c81e162554b45fd94f45132c7d15772749750e Mon Sep 17 00:00:00 2001 From: Sanjay Patel Date: Mon, 5 Aug 2019 16:59:58 +0000 Subject: [PATCH] [InstCombine] combine mul+shl separated by zext This appears to slightly help patterns similar to what's shown in PR42874: https://bugs.llvm.org/show_bug.cgi?id=42874 ...but not in the way requested. That fix will require some later IR and/or backend pass to decompose multiply/shifts into something more optimal per target. Those transforms already exist in some basic forms, but probably need enhancing to catch more cases. https://rise4fun.com/Alive/Qzv2 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@367891 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Transforms/InstCombine/InstCombineShifts.cpp | 15 +++++++++++++-- test/Transforms/InstCombine/shift.ll | 14 ++++++-------- 2 files changed, 19 insertions(+), 10 deletions(-) diff --git a/lib/Transforms/InstCombine/InstCombineShifts.cpp b/lib/Transforms/InstCombine/InstCombineShifts.cpp index a30bcbd64ca..c0a1df6b9a7 100644 --- a/lib/Transforms/InstCombine/InstCombineShifts.cpp +++ b/lib/Transforms/InstCombine/InstCombineShifts.cpp @@ -715,14 +715,25 @@ Instruction *InstCombiner::visitShl(BinaryOperator &I) { unsigned ShAmt = ShAmtAPInt->getZExtValue(); unsigned BitWidth = Ty->getScalarSizeInBits(); - // shl (zext X), ShAmt --> zext (shl X, ShAmt) - // This is only valid if X would have zeros shifted out. Value *X; if (match(Op0, m_OneUse(m_ZExt(m_Value(X))))) { unsigned SrcWidth = X->getType()->getScalarSizeInBits(); + // shl (zext X), ShAmt --> zext (shl X, ShAmt) + // This is only valid if X would have zeros shifted out. if (ShAmt < SrcWidth && MaskedValueIsZero(X, APInt::getHighBitsSet(SrcWidth, ShAmt), 0, &I)) return new ZExtInst(Builder.CreateShl(X, ShAmt), Ty); + + // shl (zext (mul MulOp, C2)), ShAmt --> mul (zext MulOp), (C2 << ShAmt) + // This is valid if the high bits of the wider multiply are shifted out. + Value *MulOp; + const APInt *C2; + if (ShAmt >= (BitWidth - SrcWidth) && + match(X, m_Mul(m_Value(MulOp), m_APInt(C2)))) { + Value *Zext = Builder.CreateZExt(MulOp, Ty); + Constant *NewMulC = ConstantInt::get(Ty, C2->zext(BitWidth).shl(ShAmt)); + return BinaryOperator::CreateMul(Zext, NewMulC); + } } // (X >> C) << C --> X & (-1 << C) diff --git a/test/Transforms/InstCombine/shift.ll b/test/Transforms/InstCombine/shift.ll index a0e6bbe33ee..4a09b15d82b 100644 --- a/test/Transforms/InstCombine/shift.ll +++ b/test/Transforms/InstCombine/shift.ll @@ -1223,9 +1223,8 @@ define <2 x i64> @shl_zext_splat_vec(<2 x i32> %t) { define i64 @shl_zext_mul(i32 %t) { ; CHECK-LABEL: @shl_zext_mul( -; CHECK-NEXT: [[MUL:%.*]] = mul i32 [[T:%.*]], 16777215 -; CHECK-NEXT: [[EXT:%.*]] = zext i32 [[MUL]] to i64 -; CHECK-NEXT: [[SHL:%.*]] = shl nuw i64 [[EXT]], 32 +; CHECK-NEXT: [[TMP1:%.*]] = zext i32 [[T:%.*]] to i64 +; CHECK-NEXT: [[SHL:%.*]] = mul i64 [[TMP1]], 72057589742960640 ; CHECK-NEXT: ret i64 [[SHL]] ; %mul = mul i32 %t, 16777215 @@ -1236,9 +1235,8 @@ define i64 @shl_zext_mul(i32 %t) { define <3 x i17> @shl_zext_mul_splat(<3 x i5> %t) { ; CHECK-LABEL: @shl_zext_mul_splat( -; CHECK-NEXT: [[MUL:%.*]] = mul <3 x i5> [[T:%.*]], -; CHECK-NEXT: [[EXT:%.*]] = zext <3 x i5> [[MUL]] to <3 x i17> -; CHECK-NEXT: [[SHL:%.*]] = shl nuw <3 x i17> [[EXT]], +; CHECK-NEXT: [[TMP1:%.*]] = zext <3 x i5> [[T:%.*]] to <3 x i17> +; CHECK-NEXT: [[SHL:%.*]] = mul <3 x i17> [[TMP1]], ; CHECK-NEXT: ret <3 x i17> [[SHL]] ; %mul = mul <3 x i5> %t, @@ -1281,8 +1279,8 @@ define i64 @shl_zext_mul_extra_use2(i32 %t) { ; CHECK-LABEL: @shl_zext_mul_extra_use2( ; CHECK-NEXT: [[MUL:%.*]] = mul i32 [[T:%.*]], 16777215 ; CHECK-NEXT: call void @use_i32(i32 [[MUL]]) -; CHECK-NEXT: [[EXT:%.*]] = zext i32 [[MUL]] to i64 -; CHECK-NEXT: [[SHL:%.*]] = shl nuw i64 [[EXT]], 32 +; CHECK-NEXT: [[TMP1:%.*]] = zext i32 [[T]] to i64 +; CHECK-NEXT: [[SHL:%.*]] = mul i64 [[TMP1]], 72057589742960640 ; CHECK-NEXT: ret i64 [[SHL]] ; %mul = mul i32 %t, 16777215 -- 2.50.1