From 88afddf69a0a0a0bde834dec247e9cee2033c02c Mon Sep 17 00:00:00 2001
From: Simon Pilgrim <llvm-dev@redking.me.uk>
Date: Fri, 2 Dec 2016 17:16:21 +0000
Subject: [PATCH] [InstCombine] Add vector urem tests

Demonstrate missed opportunity for urem -> and combine for powerof2 or zero non-uniform constant dividers

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288510 91177308-0d34-0410-b5e6-96231b3b80d8
---
 test/Transforms/InstCombine/vector-urem.ll | 29 ++++++++++++++++++++++
 1 file changed, 29 insertions(+)
 create mode 100644 test/Transforms/InstCombine/vector-urem.ll

diff --git a/test/Transforms/InstCombine/vector-urem.ll b/test/Transforms/InstCombine/vector-urem.ll
new file mode 100644
index 00000000000..6cecc16069d
--- /dev/null
+++ b/test/Transforms/InstCombine/vector-urem.ll
@@ -0,0 +1,29 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -instcombine -S | FileCheck %s
+
+define <4 x i32> @test_v4i32_splatconst_pow2(<4 x i32> %a0) {
+; CHECK-LABEL: @test_v4i32_splatconst_pow2(
+; CHECK-NEXT:    [[TMP1:%.*]] = and <4 x i32> %a0, <i32 1, i32 1, i32 1, i32 1>
+; CHECK-NEXT:    ret <4 x i32> [[TMP1]]
+;
+  %1 = urem <4 x i32> %a0, <i32 2, i32 2, i32 2, i32 2>
+  ret <4 x i32> %1
+}
+
+define <4 x i32> @test_v4i32_const_pow2(<4 x i32> %a0) {
+; CHECK-LABEL: @test_v4i32_const_pow2(
+; CHECK-NEXT:    [[TMP1:%.*]] = urem <4 x i32> %a0, <i32 1, i32 2, i32 4, i32 8>
+; CHECK-NEXT:    ret <4 x i32> [[TMP1]]
+;
+  %1 = urem <4 x i32> %a0, <i32 1, i32 2, i32 4, i32 8>
+  ret <4 x i32> %1
+}
+
+define <4 x i32> @test_v4i32_const_pow2_or_zero(<4 x i32> %a0) {
+; CHECK-LABEL: @test_v4i32_const_pow2_or_zero(
+; CHECK-NEXT:    [[TMP1:%.*]] = urem <4 x i32> %a0, <i32 1, i32 2, i32 0, i32 8>
+; CHECK-NEXT:    ret <4 x i32> [[TMP1]]
+;
+  %1 = urem <4 x i32> %a0, <i32 1, i32 2, i32 0, i32 8>
+  ret <4 x i32> %1
+}
-- 
2.50.1