From 88a7ff46b18c0435aa6f69e57d12735ef59b1a69 Mon Sep 17 00:00:00 2001 From: Krzysztof Parzyszek Date: Fri, 3 Mar 2017 18:30:54 +0000 Subject: [PATCH] Make TargetInstrInfo::isPredicable take a const reference, NFC git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296901 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/Target/TargetInstrInfo.h | 2 +- lib/Target/AMDGPU/R600InstrInfo.cpp | 4 ++-- lib/Target/AMDGPU/R600InstrInfo.h | 2 +- lib/Target/ARM/ARMBaseInstrInfo.cpp | 6 +++--- lib/Target/ARM/ARMBaseInstrInfo.h | 2 +- lib/Target/ARM/ARMFeatures.h | 4 ++-- lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 2 +- lib/Target/Hexagon/HexagonInstrInfo.cpp | 2 +- lib/Target/Hexagon/HexagonInstrInfo.h | 2 +- lib/Target/PowerPC/PPCInstrInfo.cpp | 2 +- lib/Target/PowerPC/PPCInstrInfo.h | 2 +- lib/Target/SystemZ/SystemZInstrInfo.cpp | 2 +- lib/Target/SystemZ/SystemZInstrInfo.h | 2 +- 13 files changed, 17 insertions(+), 17 deletions(-) diff --git a/include/llvm/Target/TargetInstrInfo.h b/include/llvm/Target/TargetInstrInfo.h index 4cb61feca88..f32b558a257 100644 --- a/include/llvm/Target/TargetInstrInfo.h +++ b/include/llvm/Target/TargetInstrInfo.h @@ -1142,7 +1142,7 @@ public: /// Return true if the specified instruction can be predicated. /// By default, this returns true for every instruction with a /// PredicateOperand. - virtual bool isPredicable(MachineInstr &MI) const { + virtual bool isPredicable(const MachineInstr &MI) const { return MI.getDesc().isPredicable(); } diff --git a/lib/Target/AMDGPU/R600InstrInfo.cpp b/lib/Target/AMDGPU/R600InstrInfo.cpp index 3cd98305663..1f26a8a029a 100644 --- a/lib/Target/AMDGPU/R600InstrInfo.cpp +++ b/lib/Target/AMDGPU/R600InstrInfo.cpp @@ -869,7 +869,7 @@ bool R600InstrInfo::isPredicated(const MachineInstr &MI) const { } } -bool R600InstrInfo::isPredicable(MachineInstr &MI) const { +bool R600InstrInfo::isPredicable(const MachineInstr &MI) const { // XXX: KILL* instructions can be predicated, but they must be the last // instruction in a clause, so this means any instructions after them cannot // be predicated. Until we have proper support for instruction clauses in the @@ -880,7 +880,7 @@ bool R600InstrInfo::isPredicable(MachineInstr &MI) const { } else if (MI.getOpcode() == AMDGPU::CF_ALU) { // If the clause start in the middle of MBB then the MBB has more // than a single clause, unable to predicate several clauses. - if (MI.getParent()->begin() != MachineBasicBlock::iterator(MI)) + if (MI.getParent()->begin() != MachineBasicBlock::const_iterator(MI)) return false; // TODO: We don't support KC merging atm return MI.getOperand(3).getImm() == 0 && MI.getOperand(4).getImm() == 0; diff --git a/lib/Target/AMDGPU/R600InstrInfo.h b/lib/Target/AMDGPU/R600InstrInfo.h index a280052dbd4..e05fda2be88 100644 --- a/lib/Target/AMDGPU/R600InstrInfo.h +++ b/lib/Target/AMDGPU/R600InstrInfo.h @@ -177,7 +177,7 @@ public: bool isPredicated(const MachineInstr &MI) const override; - bool isPredicable(MachineInstr &MI) const override; + bool isPredicable(const MachineInstr &MI) const override; bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCyles, BranchProbability Probability) const override; diff --git a/lib/Target/ARM/ARMBaseInstrInfo.cpp b/lib/Target/ARM/ARMBaseInstrInfo.cpp index 54b2c83fbda..38d0fd38657 100644 --- a/lib/Target/ARM/ARMBaseInstrInfo.cpp +++ b/lib/Target/ARM/ARMBaseInstrInfo.cpp @@ -597,7 +597,7 @@ static bool isEligibleForITBlock(const MachineInstr *MI) { /// isPredicable - Return true if the specified instruction can be predicated. /// By default, this returns true for every instruction with a /// PredicateOperand. -bool ARMBaseInstrInfo::isPredicable(MachineInstr &MI) const { +bool ARMBaseInstrInfo::isPredicable(const MachineInstr &MI) const { if (!MI.isPredicable()) return false; @@ -607,7 +607,7 @@ bool ARMBaseInstrInfo::isPredicable(MachineInstr &MI) const { if (!isEligibleForITBlock(&MI)) return false; - ARMFunctionInfo *AFI = + const ARMFunctionInfo *AFI = MI.getParent()->getParent()->getInfo(); if (AFI->isThumb2Function()) { @@ -623,7 +623,7 @@ bool ARMBaseInstrInfo::isPredicable(MachineInstr &MI) const { namespace llvm { -template <> bool IsCPSRDead(MachineInstr *MI) { +template <> bool IsCPSRDead(const MachineInstr *MI) { for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { const MachineOperand &MO = MI->getOperand(i); if (!MO.isReg() || MO.isUndef() || MO.isUse()) diff --git a/lib/Target/ARM/ARMBaseInstrInfo.h b/lib/Target/ARM/ARMBaseInstrInfo.h index c9ef1829e3f..d917c09140b 100644 --- a/lib/Target/ARM/ARMBaseInstrInfo.h +++ b/lib/Target/ARM/ARMBaseInstrInfo.h @@ -163,7 +163,7 @@ public: bool DefinesPredicate(MachineInstr &MI, std::vector &Pred) const override; - bool isPredicable(MachineInstr &MI) const override; + bool isPredicable(const MachineInstr &MI) const override; /// GetInstSize - Returns the size of the specified MachineInstr. /// diff --git a/lib/Target/ARM/ARMFeatures.h b/lib/Target/ARM/ARMFeatures.h index 0c910ab6130..8c0df4c2cbf 100644 --- a/lib/Target/ARM/ARMFeatures.h +++ b/lib/Target/ARM/ARMFeatures.h @@ -19,10 +19,10 @@ namespace llvm { template // could be MachineInstr or MCInst -bool IsCPSRDead(InstrType *Instr); +bool IsCPSRDead(const InstrType *Instr); template // could be MachineInstr or MCInst -inline bool isV8EligibleForIT(InstrType *Instr) { +inline bool isV8EligibleForIT(const InstrType *Instr) { switch (Instr->getOpcode()) { default: return false; diff --git a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp index c7d0709a1a7..de3b51ca5c7 100644 --- a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp +++ b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp @@ -8985,7 +8985,7 @@ unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) { } namespace llvm { -template <> inline bool IsCPSRDead(MCInst *Instr) { +template <> inline bool IsCPSRDead(const MCInst *Instr) { return true; // In an assembly source, no need to second-guess } } diff --git a/lib/Target/Hexagon/HexagonInstrInfo.cpp b/lib/Target/Hexagon/HexagonInstrInfo.cpp index 509d838ad11..ee49a080435 100644 --- a/lib/Target/Hexagon/HexagonInstrInfo.cpp +++ b/lib/Target/Hexagon/HexagonInstrInfo.cpp @@ -1434,7 +1434,7 @@ bool HexagonInstrInfo::DefinesPredicate( return false; } -bool HexagonInstrInfo::isPredicable(MachineInstr &MI) const { +bool HexagonInstrInfo::isPredicable(const MachineInstr &MI) const { return MI.getDesc().isPredicable(); } diff --git a/lib/Target/Hexagon/HexagonInstrInfo.h b/lib/Target/Hexagon/HexagonInstrInfo.h index 2358d4b7e4c..c1eb2165ce7 100644 --- a/lib/Target/Hexagon/HexagonInstrInfo.h +++ b/lib/Target/Hexagon/HexagonInstrInfo.h @@ -235,7 +235,7 @@ public: /// Return true if the specified instruction can be predicated. /// By default, this returns true for every instruction with a /// PredicateOperand. - bool isPredicable(MachineInstr &MI) const override; + bool isPredicable(const MachineInstr &MI) const override; /// Test if the given instruction should be considered a scheduling boundary. /// This primarily includes labels and terminators. diff --git a/lib/Target/PowerPC/PPCInstrInfo.cpp b/lib/Target/PowerPC/PPCInstrInfo.cpp index 92fb2269427..6c148a3a646 100644 --- a/lib/Target/PowerPC/PPCInstrInfo.cpp +++ b/lib/Target/PowerPC/PPCInstrInfo.cpp @@ -1493,7 +1493,7 @@ bool PPCInstrInfo::DefinesPredicate(MachineInstr &MI, return Found; } -bool PPCInstrInfo::isPredicable(MachineInstr &MI) const { +bool PPCInstrInfo::isPredicable(const MachineInstr &MI) const { unsigned OpC = MI.getOpcode(); switch (OpC) { default: diff --git a/lib/Target/PowerPC/PPCInstrInfo.h b/lib/Target/PowerPC/PPCInstrInfo.h index 32b2f009a3f..f11aed8fa26 100644 --- a/lib/Target/PowerPC/PPCInstrInfo.h +++ b/lib/Target/PowerPC/PPCInstrInfo.h @@ -253,7 +253,7 @@ public: bool DefinesPredicate(MachineInstr &MI, std::vector &Pred) const override; - bool isPredicable(MachineInstr &MI) const override; + bool isPredicable(const MachineInstr &MI) const override; // Comparison optimization. diff --git a/lib/Target/SystemZ/SystemZInstrInfo.cpp b/lib/Target/SystemZ/SystemZInstrInfo.cpp index 0e2ed598865..16ffd04dcb0 100644 --- a/lib/Target/SystemZ/SystemZInstrInfo.cpp +++ b/lib/Target/SystemZ/SystemZInstrInfo.cpp @@ -727,7 +727,7 @@ bool SystemZInstrInfo::FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, return true; } -bool SystemZInstrInfo::isPredicable(MachineInstr &MI) const { +bool SystemZInstrInfo::isPredicable(const MachineInstr &MI) const { unsigned Opcode = MI.getOpcode(); if (Opcode == SystemZ::Return || Opcode == SystemZ::Trap || diff --git a/lib/Target/SystemZ/SystemZInstrInfo.h b/lib/Target/SystemZ/SystemZInstrInfo.h index b07f101d4cb..3fb7880cfee 100644 --- a/lib/Target/SystemZ/SystemZInstrInfo.h +++ b/lib/Target/SystemZ/SystemZInstrInfo.h @@ -215,7 +215,7 @@ public: unsigned FalseReg) const override; bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, unsigned Reg, MachineRegisterInfo *MRI) const override; - bool isPredicable(MachineInstr &MI) const override; + bool isPredicable(const MachineInstr &MI) const override; bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const override; -- 2.50.1