From 87fd46af9024ab56a9679ce32aed0965bab69d56 Mon Sep 17 00:00:00 2001 From: Stanislav Mekhanoshin Date: Thu, 11 May 2017 17:16:55 +0000 Subject: [PATCH] [AMDGPU] Fix incorrect register pressure calculation Earlier fix D32572 introduced a bug where live-ins were calculated for basic block instead of scheduling region. This change fixes it. Differential Revision: https://reviews.llvm.org/D33086 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302812 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/AMDGPU/GCNSchedStrategy.cpp | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/lib/Target/AMDGPU/GCNSchedStrategy.cpp b/lib/Target/AMDGPU/GCNSchedStrategy.cpp index 630442625aa..9f07d28c708 100644 --- a/lib/Target/AMDGPU/GCNSchedStrategy.cpp +++ b/lib/Target/AMDGPU/GCNSchedStrategy.cpp @@ -422,9 +422,10 @@ void GCNScheduleDAGMILive::discoverLiveIns() { unsigned SGPRs = 0; unsigned VGPRs = 0; - auto &MI = *begin()->getParent()->getFirstNonDebugInstr(); + auto I = begin(); + I = skipDebugInstructionsForward(I, I->getParent()->end()); const SIRegisterInfo *SRI = static_cast(TRI); - SlotIndex SI = LIS->getInstructionIndex(MI).getBaseIndex(); + SlotIndex SI = LIS->getInstructionIndex(*I).getBaseIndex(); assert (SI.isValid()); DEBUG(dbgs() << "Region live-ins:"); -- 2.40.0