From 87f9f81250e3483a17ac0df4c9d24db7ef691fc8 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Mon, 1 Jul 2019 16:36:39 +0000 Subject: [PATCH] AMDGPU/GlobalISel: Fail instead of assert when selecting loads git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364807 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) diff --git a/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp index f64da2d4884..bd4c73ef3c9 100644 --- a/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp +++ b/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp @@ -1036,25 +1036,31 @@ bool AMDGPUInstructionSelector::selectG_LOAD(MachineInstr &I) const { MachineBasicBlock *BB = I.getParent(); MachineFunction *MF = BB->getParent(); MachineRegisterInfo &MRI = MF->getRegInfo(); - DebugLoc DL = I.getDebugLoc(); - unsigned DstReg = I.getOperand(0).getReg(); - unsigned PtrReg = I.getOperand(1).getReg(); + const DebugLoc &DL = I.getDebugLoc(); + Register DstReg = I.getOperand(0).getReg(); + Register PtrReg = I.getOperand(1).getReg(); unsigned LoadSize = RBI.getSizeInBits(DstReg, MRI, TRI); unsigned Opcode; + if (MRI.getType(I.getOperand(1).getReg()).getSizeInBits() == 32) { + LLVM_DEBUG(dbgs() << "Unhandled address space\n"); + return false; + } + SmallVector AddrInfo; getAddrModeInfo(I, MRI, AddrInfo); switch (LoadSize) { - default: - llvm_unreachable("Load size not supported\n"); case 32: Opcode = AMDGPU::FLAT_LOAD_DWORD; break; case 64: Opcode = AMDGPU::FLAT_LOAD_DWORDX2; break; + default: + LLVM_DEBUG(dbgs() << "Unhandled load size\n"); + return false; } MachineInstr *Flat = BuildMI(*BB, &I, DL, TII.get(Opcode)) -- 2.40.0