From 854b0aaa85f85d60a06f1944c86ee75770a913d9 Mon Sep 17 00:00:00 2001 From: Tom Stellard Date: Thu, 23 Apr 2015 19:14:38 +0000 Subject: [PATCH] Merging r229223: ------------------------------------------------------------------------ r229223 | Matthew.Arsenault | 2015-02-13 21:51:44 -0500 (Fri, 13 Feb 2015) | 5 lines R600/SI: Fix size of VReg_1 This is really a 32-bit register, if we try to check the size of it, we want 32-bits. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@235621 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/R600/SIRegisterInfo.td | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/Target/R600/SIRegisterInfo.td b/lib/Target/R600/SIRegisterInfo.td index 1a1efb0c89a..8d0312349aa 100644 --- a/lib/Target/R600/SIRegisterInfo.td +++ b/lib/Target/R600/SIRegisterInfo.td @@ -209,7 +209,7 @@ def VReg_256 : RegisterClass<"AMDGPU", [v32i8, v8i32, v8f32], 256, (add VGPR_256 def VReg_512 : RegisterClass<"AMDGPU", [v16i32, v16f32], 512, (add VGPR_512)>; -def VReg_1 : RegisterClass<"AMDGPU", [i1], 32, (add VGPR_32)>; +def VReg_1 : RegisterClass<"AMDGPU", [i1, i32], 32, (add VGPR_32)>; class RegImmOperand : RegisterOperand { let OperandNamespace = "AMDGPU"; -- 2.50.1