From 84d1605bd4a8e020373c64938f8b942d14df1b0f Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Thu, 20 Dec 2018 10:54:59 +0000 Subject: [PATCH] [X86] Change 'simple nonmem' intrinsic test to not use PADDSW Those intrinsics will be autoupgraded soon to @llvm.sadd.sat generics (D55894), so to keep a x86-specific case I'm replacing it with @llvm.x86.sse2.pmulhu.w git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@349739 91177308-0d34-0410-b5e6-96231b3b80d8 --- .../MemorySanitizer/msan_x86intrinsics.ll | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/test/Instrumentation/MemorySanitizer/msan_x86intrinsics.ll b/test/Instrumentation/MemorySanitizer/msan_x86intrinsics.ll index c4ec7fa2919..14aaec92388 100644 --- a/test/Instrumentation/MemorySanitizer/msan_x86intrinsics.ll +++ b/test/Instrumentation/MemorySanitizer/msan_x86intrinsics.ll @@ -46,14 +46,14 @@ declare <16 x i8> @llvm.x86.sse3.ldu.dq(i8* %p) nounwind ; Check that shadow is OR'ed, and origin is Select'ed ; And no shadow checks! -define <8 x i16> @Paddsw128(<8 x i16> %a, <8 x i16> %b) nounwind uwtable sanitize_memory { - %call = call <8 x i16> @llvm.x86.sse2.padds.w(<8 x i16> %a, <8 x i16> %b) +define <8 x i16> @Pmulhuw128(<8 x i16> %a, <8 x i16> %b) nounwind uwtable sanitize_memory { + %call = call <8 x i16> @llvm.x86.sse2.pmulhu.w(<8 x i16> %a, <8 x i16> %b) ret <8 x i16> %call } -declare <8 x i16> @llvm.x86.sse2.padds.w(<8 x i16> %a, <8 x i16> %b) nounwind +declare <8 x i16> @llvm.x86.sse2.pmulhu.w(<8 x i16> %a, <8 x i16> %b) nounwind -; CHECK-LABEL: @Paddsw128 +; CHECK-LABEL: @Pmulhuw128 ; CHECK-NEXT: load <8 x i16>, <8 x i16>* {{.*}} @__msan_param_tls ; CHECK-ORIGINS: load i32, i32* {{.*}} @__msan_param_origin_tls ; CHECK-NEXT: load <8 x i16>, <8 x i16>* {{.*}} @__msan_param_tls @@ -62,7 +62,7 @@ declare <8 x i16> @llvm.x86.sse2.padds.w(<8 x i16> %a, <8 x i16> %b) nounwind ; CHECK-ORIGINS: = bitcast <8 x i16> {{.*}} to i128 ; CHECK-ORIGINS-NEXT: = icmp ne i128 {{.*}}, 0 ; CHECK-ORIGINS-NEXT: = select i1 {{.*}}, i32 {{.*}}, i32 -; CHECK-NEXT: call <8 x i16> @llvm.x86.sse2.padds.w +; CHECK-NEXT: call <8 x i16> @llvm.x86.sse2.pmulhu.w ; CHECK-NEXT: store <8 x i16> {{.*}} @__msan_retval_tls ; CHECK-ORIGINS: store i32 {{.*}} @__msan_retval_origin_tls ; CHECK-NEXT: ret <8 x i16> -- 2.50.1