From 848abc34f519039b2db95eb5a90ac8458ca45d35 Mon Sep 17 00:00:00 2001
From: Sean Fertile <sfertile@ca.ibm.com>
Date: Mon, 15 Apr 2019 17:08:43 +0000
Subject: [PATCH] Add slbfee instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@358425 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/PowerPC/P9InstrResources.td   | 1 +
 lib/Target/PowerPC/PPCInstrFormats.td    | 1 +
 lib/Target/PowerPC/PPCInstrInfo.td       | 4 ++++
 lib/Target/PowerPC/PPCSchedule.td        | 1 +
 test/MC/PowerPC/ppc64-encoding-bookIII.s | 4 ++++
 5 files changed, 11 insertions(+)

diff --git a/lib/Target/PowerPC/P9InstrResources.td b/lib/Target/PowerPC/P9InstrResources.td
index f87959f7c5f..4443c469ae4 100644
--- a/lib/Target/PowerPC/P9InstrResources.td
+++ b/lib/Target/PowerPC/P9InstrResources.td
@@ -1405,6 +1405,7 @@ def : InstRW<[],
   MBAR,
   MSYNC,
   SLBSYNC,
+  SLBFEEo,
   NAP,
   STOP,
   TRAP,
diff --git a/lib/Target/PowerPC/PPCInstrFormats.td b/lib/Target/PowerPC/PPCInstrFormats.td
index 7091f790da5..a48eb169069 100644
--- a/lib/Target/PowerPC/PPCInstrFormats.td
+++ b/lib/Target/PowerPC/PPCInstrFormats.td
@@ -720,6 +720,7 @@ class XForm_25_memOp<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
   : XForm_base_r3xo_memOp<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
 }
 
+// [PO RT /// RB XO RC]
 class XForm_26<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
                InstrItinClass itin, list<dag> pattern>
   : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
diff --git a/lib/Target/PowerPC/PPCInstrInfo.td b/lib/Target/PowerPC/PPCInstrInfo.td
index 5b541f2bb03..55d9fa7ed67 100644
--- a/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/lib/Target/PowerPC/PPCInstrInfo.td
@@ -4092,6 +4092,10 @@ def SLBMFEV : XLForm_1_gen<31, 851, (outs gprc:$RT), (ins gprc:$RB),
 
 def SLBIA : XForm_0<31, 498, (outs), (ins), "slbia", IIC_SprSLBIA, []>;
 
+let Defs = [CR0] in
+def SLBFEEo : XForm_26<31, 979, (outs gprc:$RT), (ins gprc:$RB),
+                         "slbfee. $RT, $RB", IIC_SprSLBFEE, []>, isDOT;
+
 def TLBIA : XForm_0<31, 370, (outs), (ins),
                         "tlbia", IIC_SprTLBIA, []>;
 
diff --git a/lib/Target/PowerPC/PPCSchedule.td b/lib/Target/PowerPC/PPCSchedule.td
index 1a54975cb8f..4fa29d96ca1 100644
--- a/lib/Target/PowerPC/PPCSchedule.td
+++ b/lib/Target/PowerPC/PPCSchedule.td
@@ -105,6 +105,7 @@ def IIC_VecVSL       : InstrItinClass;
 def IIC_VecVSR       : InstrItinClass;
 def IIC_SprMTMSRD    : InstrItinClass;
 def IIC_SprSLIE      : InstrItinClass;
+def IIC_SprSLBFEE    : InstrItinClass;
 def IIC_SprSLBIE     : InstrItinClass;
 def IIC_SprSLBIEG    : InstrItinClass;
 def IIC_SprSLBMTE    : InstrItinClass;
diff --git a/test/MC/PowerPC/ppc64-encoding-bookIII.s b/test/MC/PowerPC/ppc64-encoding-bookIII.s
index a9d21b299f5..9592f425dce 100644
--- a/test/MC/PowerPC/ppc64-encoding-bookIII.s
+++ b/test/MC/PowerPC/ppc64-encoding-bookIII.s
@@ -150,6 +150,10 @@
 # CHECK-LE: slbia                           # encoding: [0xe4,0x03,0x00,0x7c]
             slbia
 
+# CHECK-BE: slbfee. 4, 5                    # encoding: [0x7c,0x80,0x2f,0xa7]
+# CHECK-LE: slbfee. 4, 5                    # encoding: [0xa7,0x2f,0x80,0x7c]
+            slbfee. %r4, %r5
+
 # CHECK-BE: tlbsync                         # encoding: [0x7c,0x00,0x04,0x6c]
 # CHECK-LE: tlbsync                         # encoding: [0x6c,0x04,0x00,0x7c]
             tlbsync
-- 
2.50.1