From 846a9882992511cc0d34aaa1b031becec3bcd80d Mon Sep 17 00:00:00 2001 From: Andrea Di Biagio Date: Mon, 18 Feb 2019 11:27:11 +0000 Subject: [PATCH] [MCA] Slightly refactor method writeStartEvent in WriteState and ReadState. NFCI This is another change in preparation for PR37494. No functional change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@354261 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/MCA/Instruction.h | 29 ++++++++++++++++---------- lib/MCA/HardwareUnits/RegisterFile.cpp | 4 ++-- lib/MCA/HardwareUnits/Scheduler.cpp | 2 +- lib/MCA/Instruction.cpp | 20 +++++++++--------- 4 files changed, 31 insertions(+), 24 deletions(-) diff --git a/include/llvm/MCA/Instruction.h b/include/llvm/MCA/Instruction.h index 658b7fe4f89..d9bf3b7fa82 100644 --- a/include/llvm/MCA/Instruction.h +++ b/include/llvm/MCA/Instruction.h @@ -150,9 +150,17 @@ public: unsigned getRegisterID() const { return RegisterID; } unsigned getRegisterFileID() const { return PRFID; } unsigned getLatency() const { return WD->Latency; } + const WriteState *getDependentWrite() const { return DependentWrite; } + + // This method adds Use to the set of data dependent reads. IID is the + // instruction identifier associated with this write. ReadAdvance is the + // number of cycles to subtract from the latency of this data dependency. + // Use is in a RAW dependency with this write. + void addUser(unsigned IID, ReadState *Use, int ReadAdvance); - void addUser(ReadState *Use, int ReadAdvance); - void addUser(WriteState *Use); + // Use is a younger register write that is in a false dependency with this + // write. IID is the instruction identifier associated with this write. + void addUser(unsigned IID, WriteState *Use); unsigned getDependentWriteCyclesLeft() const { return DependentWriteCyclesLeft; @@ -170,7 +178,7 @@ public: bool isEliminated() const { return IsEliminated; } bool isReady() const { - if (getDependentWrite()) + if (DependentWrite) return false; unsigned CyclesLeft = getDependentWriteCyclesLeft(); return !CyclesLeft || CyclesLeft < getLatency(); @@ -180,9 +188,8 @@ public: return CyclesLeft != UNKNOWN_CYCLES && CyclesLeft <= 0; } - const WriteState *getDependentWrite() const { return DependentWrite; } - void setDependentWrite(WriteState *Other) { DependentWrite = Other; } - void writeStartEvent(unsigned Cycles) { + void setDependentWrite(const WriteState *Other) { DependentWrite = Other; } + void writeStartEvent(unsigned IID, unsigned RegID, unsigned Cycles) { DependentWriteCyclesLeft = Cycles; DependentWrite = nullptr; } @@ -198,7 +205,7 @@ public: // On every cycle, update CyclesLeft and notify dependent users. void cycleEvent(); - void onInstructionIssued(); + void onInstructionIssued(unsigned IID); #ifndef NDEBUG void dump() const; @@ -255,7 +262,7 @@ public: void setIndependentFromDef() { IndependentFromDef = true; } void cycleEvent(); - void writeStartEvent(unsigned Cycles); + void writeStartEvent(unsigned IID, unsigned RegID, unsigned Cycles); void setDependentWrites(unsigned Writes) { DependentWrites = Writes; IsReady = !Writes; @@ -454,8 +461,8 @@ public: void dispatch(unsigned RCUTokenID); // Instruction issued. Transition to the IS_EXECUTING state, and update - // all the definitions. - void execute(); + // all the register definitions. + void execute(unsigned IID); // Force a transition from the IS_DISPATCHED state to the IS_READY or // IS_PENDING state. State transitions normally occur either at the beginning @@ -556,7 +563,7 @@ public: return !WS || WS->isExecuted(); } - bool isValid() const { return Data.first != INVALID_IID && Data.second; } + bool isValid() const { return Data.second && Data.first != INVALID_IID; } bool operator==(const WriteRef &Other) const { return Data == Other.Data; } #ifndef NDEBUG diff --git a/lib/MCA/HardwareUnits/RegisterFile.cpp b/lib/MCA/HardwareUnits/RegisterFile.cpp index 3621d182b3e..995c50fc6a8 100644 --- a/lib/MCA/HardwareUnits/RegisterFile.cpp +++ b/lib/MCA/HardwareUnits/RegisterFile.cpp @@ -188,7 +188,7 @@ void RegisterFile::addRegisterWrite(WriteRef Write, if (OtherWS && (OtherWrite.getSourceIndex() != Write.getSourceIndex())) { // This partial write has a false dependency on RenameAs. assert(!IsEliminated && "Unexpected partial update!"); - OtherWS->addUser(&WS); + OtherWS->addUser(OtherWrite.getSourceIndex(), &WS); } } } @@ -425,7 +425,7 @@ void RegisterFile::addRegisterRead(ReadState &RS, WriteState &WS = *WR.getWriteState(); unsigned WriteResID = WS.getWriteResourceID(); int ReadAdvance = STI.getReadAdvanceCycles(SC, RD.UseIndex, WriteResID); - WS.addUser(&RS, ReadAdvance); + WS.addUser(WR.getSourceIndex(), &RS, ReadAdvance); } } diff --git a/lib/MCA/HardwareUnits/Scheduler.cpp b/lib/MCA/HardwareUnits/Scheduler.cpp index b5f3617b08f..33db5d24f64 100644 --- a/lib/MCA/HardwareUnits/Scheduler.cpp +++ b/lib/MCA/HardwareUnits/Scheduler.cpp @@ -74,7 +74,7 @@ void Scheduler::issueInstructionImpl( // Notify the instruction that it started executing. // This updates the internal state of each write. - IS->execute(); + IS->execute(IR.getSourceIndex()); if (IS->isExecuting()) IssuedSet.emplace_back(IR); diff --git a/lib/MCA/Instruction.cpp b/lib/MCA/Instruction.cpp index b1508a0ade0..58f02503137 100644 --- a/lib/MCA/Instruction.cpp +++ b/lib/MCA/Instruction.cpp @@ -18,7 +18,7 @@ namespace llvm { namespace mca { -void ReadState::writeStartEvent(unsigned Cycles) { +void ReadState::writeStartEvent(unsigned IID, unsigned RegID, unsigned Cycles) { assert(DependentWrites); assert(CyclesLeft == UNKNOWN_CYCLES); @@ -36,7 +36,7 @@ void ReadState::writeStartEvent(unsigned Cycles) { } } -void WriteState::onInstructionIssued() { +void WriteState::onInstructionIssued(unsigned IID) { assert(CyclesLeft == UNKNOWN_CYCLES); // Update the number of cycles left based on the WriteDescriptor info. CyclesLeft = getLatency(); @@ -46,30 +46,30 @@ void WriteState::onInstructionIssued() { for (const std::pair &User : Users) { ReadState *RS = User.first; unsigned ReadCycles = std::max(0, CyclesLeft - User.second); - RS->writeStartEvent(ReadCycles); + RS->writeStartEvent(IID, RegisterID, ReadCycles); } // Notify any writes that are in a false dependency with this write. if (PartialWrite) - PartialWrite->writeStartEvent(CyclesLeft); + PartialWrite->writeStartEvent(IID, RegisterID, CyclesLeft); } -void WriteState::addUser(ReadState *User, int ReadAdvance) { +void WriteState::addUser(unsigned IID, ReadState *User, int ReadAdvance) { // If CyclesLeft is different than -1, then we don't need to // update the list of users. We can just notify the user with // the actual number of cycles left (which may be zero). if (CyclesLeft != UNKNOWN_CYCLES) { unsigned ReadCycles = std::max(0, CyclesLeft - ReadAdvance); - User->writeStartEvent(ReadCycles); + User->writeStartEvent(IID, RegisterID, ReadCycles); return; } Users.emplace_back(User, ReadAdvance); } -void WriteState::addUser(WriteState *User) { +void WriteState::addUser(unsigned IID, WriteState *User) { if (CyclesLeft != UNKNOWN_CYCLES) { - User->writeStartEvent(std::max(0, CyclesLeft)); + User->writeStartEvent(IID, RegisterID, std::max(0, CyclesLeft)); return; } @@ -131,7 +131,7 @@ void Instruction::dispatch(unsigned RCUToken) { updatePending(); } -void Instruction::execute() { +void Instruction::execute(unsigned IID) { assert(Stage == IS_READY); Stage = IS_EXECUTING; @@ -139,7 +139,7 @@ void Instruction::execute() { CyclesLeft = getLatency(); for (WriteState &WS : getDefs()) - WS.onInstructionIssued(); + WS.onInstructionIssued(IID); // Transition to the "executed" stage if this is a zero-latency instruction. if (!CyclesLeft) -- 2.40.0