From 8419f9e400d3d1e15101ae42f0db2d9bd1095fc3 Mon Sep 17 00:00:00 2001 From: Jonas Paulsson Date: Fri, 31 Mar 2017 14:06:59 +0000 Subject: [PATCH] [SystemZ] Make sure of correct regclasses in insertSelect() Since LOCR only accepts GR32 virtual registers, its operands must be copied into this regclass in insertSelect(), when an LOCR is built. Otherwise, the case where the source operand was GRX32 will produce invalid IR. Review: Ulrich Weigand git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299220 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/SystemZ/SystemZInstrInfo.cpp | 6 ++++++ test/CodeGen/SystemZ/locr-legal-regclass.ll | 20 ++++++++++++++++++++ 2 files changed, 26 insertions(+) create mode 100644 test/CodeGen/SystemZ/locr-legal-regclass.ll diff --git a/lib/Target/SystemZ/SystemZInstrInfo.cpp b/lib/Target/SystemZ/SystemZInstrInfo.cpp index f3eed05e88e..c8ff9558cc8 100644 --- a/lib/Target/SystemZ/SystemZInstrInfo.cpp +++ b/lib/Target/SystemZ/SystemZInstrInfo.cpp @@ -679,6 +679,12 @@ void SystemZInstrInfo::insertSelect(MachineBasicBlock &MBB, else { Opc = SystemZ::LOCR; MRI.constrainRegClass(DstReg, &SystemZ::GR32BitRegClass); + unsigned TReg = MRI.createVirtualRegister(&SystemZ::GR32BitRegClass); + unsigned FReg = MRI.createVirtualRegister(&SystemZ::GR32BitRegClass); + BuildMI(MBB, I, DL, get(TargetOpcode::COPY), TReg).addReg(TrueReg); + BuildMI(MBB, I, DL, get(TargetOpcode::COPY), FReg).addReg(FalseReg); + TrueReg = TReg; + FalseReg = FReg; } } else if (SystemZ::GR64BitRegClass.hasSubClassEq(RC)) Opc = SystemZ::LOCGR; diff --git a/test/CodeGen/SystemZ/locr-legal-regclass.ll b/test/CodeGen/SystemZ/locr-legal-regclass.ll new file mode 100644 index 00000000000..1f792439a49 --- /dev/null +++ b/test/CodeGen/SystemZ/locr-legal-regclass.ll @@ -0,0 +1,20 @@ +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=zEC12 -verify-machineinstrs | FileCheck %s +; +; Test that early if conversion produces LOCR with operands of the right +; register classes. + +define void @autogen_SD4739(i8*) { +; CHECK-NOT: Expected a GR32Bit register, but got a GRX32Bit register +BB: + %L34 = load i8, i8* %0 + %Cmp56 = icmp sgt i8 undef, %L34 + br label %CF246 + +CF246: ; preds = %CF246, %BB + %Sl163 = select i1 %Cmp56, i8 %L34, i8 undef + br i1 undef, label %CF246, label %CF248 + +CF248: ; preds = %CF248, %CF246 + store i8 %Sl163, i8* %0 + br label %CF248 +} -- 2.50.1