From 82f8dab579d33fee96676fbee525e894928ee035 Mon Sep 17 00:00:00 2001 From: NAKAMURA Takumi Date: Mon, 20 Jun 2016 00:37:41 +0000 Subject: [PATCH] Untabify. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@273129 91177308-0d34-0410-b5e6-96231b3b80d8 --- .../AArch64/AArch64LoadStoreOptimizer.cpp | 2 +- .../Disassembler/AArch64ExternalSymbolizer.cpp | 2 +- lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp | 8 +++----- lib/Target/AMDGPU/SIISelLowering.cpp | 3 +-- lib/Target/AMDGPU/SIInstrInfo.cpp | 4 ++-- lib/Target/Mips/MipsHazardSchedule.cpp | 4 ++-- lib/Target/PowerPC/PPCISelLowering.cpp | 4 ++-- lib/Target/PowerPC/PPCQPXLoadSplat.cpp | 12 ++++++------ lib/Target/SystemZ/SystemZShortenInst.cpp | 17 +++++++++-------- 9 files changed, 27 insertions(+), 29 deletions(-) diff --git a/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp b/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp index 37d20793183..2bd655d0aa2 100644 --- a/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp +++ b/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp @@ -1682,7 +1682,7 @@ bool AArch64LoadStoreOpt::optimizeBlock(MachineBasicBlock &MBB, // ldrh w2, [x0, #6] // ; becomes // str w1, [x0, #4] - // lsr w2, w1, #16 + // lsr w2, w1, #16 for (MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end(); MBBI != E;) { MachineInstr *MI = MBBI; diff --git a/lib/Target/AArch64/Disassembler/AArch64ExternalSymbolizer.cpp b/lib/Target/AArch64/Disassembler/AArch64ExternalSymbolizer.cpp index c2ec90ffda6..19d0ba2e1c4 100644 --- a/lib/Target/AArch64/Disassembler/AArch64ExternalSymbolizer.cpp +++ b/lib/Target/AArch64/Disassembler/AArch64ExternalSymbolizer.cpp @@ -136,7 +136,7 @@ bool AArch64ExternalSymbolizer::tryAddingSymbolicOperand( else if (ReferenceType == LLVMDisassembler_ReferenceType_Out_LitPool_CstrAddr) { CommentStream << "literal pool for: \""; - CommentStream.write_escaped(ReferenceName); + CommentStream.write_escaped(ReferenceName); CommentStream << "\""; } else if (ReferenceType == LLVMDisassembler_ReferenceType_Out_Objc_CFString_Ref) diff --git a/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp b/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp index bba92c32195..3c5c188fdc1 100644 --- a/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp +++ b/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp @@ -47,8 +47,7 @@ static bool isCBranchSCC(const SDNode *N) { if (Cond.getOpcode() == ISD::CopyToReg) Cond = Cond.getOperand(2); return Cond.getOpcode() == ISD::SETCC && - Cond.getOperand(0).getValueType() == MVT::i32 && - Cond.hasOneUse(); + Cond.getOperand(0).getValueType() == MVT::i32 && Cond.hasOneUse(); } /// AMDGPU specific code to select AMDGPU machine instructions for @@ -619,9 +618,8 @@ bool AMDGPUDAGToDAGISel::isGlobalLoad(const MemSDNode *N) const { return false; if (N->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS) { if (Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS) - return !isa( - GetUnderlyingObject(N->getMemOperand()->getValue(), - CurDAG->getDataLayout())); + return !isa(GetUnderlyingObject( + N->getMemOperand()->getValue(), CurDAG->getDataLayout())); //TODO: Why do we need this? if (N->getMemoryVT().bitsLT(MVT::i32)) diff --git a/lib/Target/AMDGPU/SIISelLowering.cpp b/lib/Target/AMDGPU/SIISelLowering.cpp index 7bbbacdf5a7..7fc94911d13 100644 --- a/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/lib/Target/AMDGPU/SIISelLowering.cpp @@ -656,8 +656,7 @@ SDValue SITargetLowering::LowerFormalArguments( // enabled too. if (CallConv == CallingConv::AMDGPU_PS && ((Info->getPSInputAddr() & 0x7F) == 0 || - ((Info->getPSInputAddr() & 0xF) == 0 && - Info->isPSInputAllocated(11)))) { + ((Info->getPSInputAddr() & 0xF) == 0 && Info->isPSInputAllocated(11)))) { CCInfo.AllocateReg(AMDGPU::VGPR0); CCInfo.AllocateReg(AMDGPU::VGPR1); Info->markPSInputAllocated(0); diff --git a/lib/Target/AMDGPU/SIInstrInfo.cpp b/lib/Target/AMDGPU/SIInstrInfo.cpp index 850826d74cc..7e64cbe11ee 100644 --- a/lib/Target/AMDGPU/SIInstrInfo.cpp +++ b/lib/Target/AMDGPU/SIInstrInfo.cpp @@ -300,8 +300,8 @@ bool SIInstrInfo::getMemOpBaseRegImmOfs(MachineInstr *LdSt, unsigned &BaseReg, bool SIInstrInfo::shouldClusterMemOps(MachineInstr *FirstLdSt, MachineInstr *SecondLdSt, unsigned NumLoads) const { - const MachineOperand *FirstDst = nullptr; - const MachineOperand *SecondDst = nullptr; + const MachineOperand *FirstDst = nullptr; + const MachineOperand *SecondDst = nullptr; if (isDS(*FirstLdSt) && isDS(*SecondLdSt)) { FirstDst = getNamedOperand(*FirstLdSt, AMDGPU::OpName::vdst); diff --git a/lib/Target/Mips/MipsHazardSchedule.cpp b/lib/Target/Mips/MipsHazardSchedule.cpp index edd176548c5..c595c9b46ff 100644 --- a/lib/Target/Mips/MipsHazardSchedule.cpp +++ b/lib/Target/Mips/MipsHazardSchedule.cpp @@ -23,8 +23,8 @@ /// /// For example: /// -/// 0x8004 bnec a1,v0, -/// 0x8008 beqc a1,a2, +/// 0x8004 bnec a1,v0, +/// 0x8008 beqc a1,a2, /// /// In such cases, the processor is required to signal a Reserved Instruction /// exception. diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp index 22ae871dc6b..b9e1a268626 100644 --- a/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/lib/Target/PowerPC/PPCISelLowering.cpp @@ -10588,8 +10588,8 @@ SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N, MinAlign(LD->getAlignment(), 4), LD->getAAInfo()); if (LD->isIndexed()) { - // Note that DAGCombine should re-form any pre-increment load(s) from - // what is produced here if that makes sense. + // Note that DAGCombine should re-form any pre-increment load(s) from + // what is produced here if that makes sense. DAG.ReplaceAllUsesOfValueWith(SDValue(LD, 1), BasePtr); } diff --git a/lib/Target/PowerPC/PPCQPXLoadSplat.cpp b/lib/Target/PowerPC/PPCQPXLoadSplat.cpp index 816f05f4bf6..d233cd28a50 100644 --- a/lib/Target/PowerPC/PPCQPXLoadSplat.cpp +++ b/lib/Target/PowerPC/PPCQPXLoadSplat.cpp @@ -130,12 +130,12 @@ bool PPCQPXLoadSplat::runOnMachineFunction(MachineFunction &MF) { } } - // If this instruction defines the splat register, then we cannot move - // the previous definition above it. If it reads from the splat - // register, then it must already be alive from some previous - // definition, and if the splat register is different from the source - // register, then this definition must not be the load for which we're - // searching. + // If this instruction defines the splat register, then we cannot move + // the previous definition above it. If it reads from the splat + // register, then it must already be alive from some previous + // definition, and if the splat register is different from the source + // register, then this definition must not be the load for which we're + // searching. if (MI->modifiesRegister(SplatReg, TRI) || (SrcReg != SplatReg && MI->readsRegister(SplatReg, TRI))) { diff --git a/lib/Target/SystemZ/SystemZShortenInst.cpp b/lib/Target/SystemZ/SystemZShortenInst.cpp index 083718518f2..65bd3f0a214 100644 --- a/lib/Target/SystemZ/SystemZShortenInst.cpp +++ b/lib/Target/SystemZ/SystemZShortenInst.cpp @@ -78,12 +78,14 @@ bool SystemZShortenInst::shortenIIF(MachineInstr &MI, unsigned Reg = MI.getOperand(0).getReg(); // The new opcode will clear the other half of the GR64 reg, so // cancel if that is live. - unsigned thisSubRegIdx = (SystemZ::GRH32BitRegClass.contains(Reg) ? - SystemZ::subreg_h32 : SystemZ::subreg_l32); - unsigned otherSubRegIdx = (thisSubRegIdx == SystemZ::subreg_l32 ? - SystemZ::subreg_h32 : SystemZ::subreg_l32); - unsigned GR64BitReg = TRI->getMatchingSuperReg(Reg, thisSubRegIdx, - &SystemZ::GR64BitRegClass); + unsigned thisSubRegIdx = + (SystemZ::GRH32BitRegClass.contains(Reg) ? SystemZ::subreg_h32 + : SystemZ::subreg_l32); + unsigned otherSubRegIdx = + (thisSubRegIdx == SystemZ::subreg_l32 ? SystemZ::subreg_h32 + : SystemZ::subreg_l32); + unsigned GR64BitReg = + TRI->getMatchingSuperReg(Reg, thisSubRegIdx, &SystemZ::GR64BitRegClass); unsigned OtherReg = TRI->getSubReg(GR64BitReg, otherSubRegIdx); if (LiveRegs.contains(OtherReg)) return false; @@ -139,8 +141,7 @@ bool SystemZShortenInst::shortenOn001(MachineInstr &MI, unsigned Opcode) { // Calls shortenOn001 if CCLive is false. CC def operand is added in // case of success. -bool SystemZShortenInst::shortenOn001AddCC(MachineInstr &MI, - unsigned Opcode) { +bool SystemZShortenInst::shortenOn001AddCC(MachineInstr &MI, unsigned Opcode) { if (!LiveRegs.contains(SystemZ::CC) && shortenOn001(MI, Opcode)) { MachineInstrBuilder(*MI.getParent()->getParent(), &MI) .addReg(SystemZ::CC, RegState::ImplicitDefine | RegState::Dead); -- 2.50.1