From 80b0a9b94f5fe98973343a7ba01b69fdb929f321 Mon Sep 17 00:00:00 2001 From: Momchil Velikov Date: Wed, 17 Jul 2019 17:43:32 +0000 Subject: [PATCH] Revert [AArch64] Add support for Transactional Memory Extension (TME) This reverts r366322 (git commit 4b8da3a503e434ddbc08ecf66582475765f449bc) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366355 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/IR/IntrinsicsAArch64.td | 17 ------ include/llvm/Support/AArch64TargetParser.def | 1 - include/llvm/Support/AArch64TargetParser.h | 1 - lib/Target/AArch64/AArch64.td | 3 -- lib/Target/AArch64/AArch64InstrFormats.td | 55 +++----------------- lib/Target/AArch64/AArch64InstrInfo.td | 29 +++-------- lib/Target/AArch64/AArch64Subtarget.h | 2 - test/CodeGen/AArch64/tme-tcancel.ll | 16 ------ test/CodeGen/AArch64/tme-tcommit.ll | 16 ------ test/CodeGen/AArch64/tme-tstart.ll | 16 ------ test/CodeGen/AArch64/tme-ttest.ll | 16 ------ test/MC/AArch64/tme-error.s | 47 ----------------- test/MC/AArch64/tme.s | 24 --------- test/MC/Disassembler/AArch64/tme.txt | 19 ------- unittests/Support/TargetParserTest.cpp | 1 - 15 files changed, 12 insertions(+), 251 deletions(-) delete mode 100644 test/CodeGen/AArch64/tme-tcancel.ll delete mode 100644 test/CodeGen/AArch64/tme-tcommit.ll delete mode 100644 test/CodeGen/AArch64/tme-tstart.ll delete mode 100644 test/CodeGen/AArch64/tme-ttest.ll delete mode 100644 test/MC/AArch64/tme-error.s delete mode 100644 test/MC/AArch64/tme.s delete mode 100644 test/MC/Disassembler/AArch64/tme.txt diff --git a/include/llvm/IR/IntrinsicsAArch64.td b/include/llvm/IR/IntrinsicsAArch64.td index ceec212b663..7616d6a90c1 100644 --- a/include/llvm/IR/IntrinsicsAArch64.td +++ b/include/llvm/IR/IntrinsicsAArch64.td @@ -703,20 +703,3 @@ def int_aarch64_stg : Intrinsic<[], [llvm_ptr_ty, llvm_ptr_ty], def int_aarch64_subp : Intrinsic<[llvm_i64_ty], [llvm_ptr_ty, llvm_ptr_ty], [IntrNoMem]>; } - -// Transactional Memory Extension (TME) Intrinsics -let TargetPrefix = "aarch64" in { -def int_aarch64_tstart : GCCBuiltin<"__builtin_arm_tstart">, - Intrinsic<[llvm_i64_ty]>; - -def int_aarch64_tcommit : GCCBuiltin<"__builtin_arm_tcommit">, Intrinsic<[]>; - -def int_aarch64_tcancel : GCCBuiltin<"__builtin_arm_tcancel">, - Intrinsic<[], [llvm_i64_ty], - [ImmArg<0>, IntrNoMem, IntrHasSideEffects, - IntrNoReturn]>; - -def int_aarch64_ttest : GCCBuiltin<"__builtin_arm_ttest">, - Intrinsic<[llvm_i64_ty], [], - [IntrNoMem, IntrHasSideEffects]>; -} diff --git a/include/llvm/Support/AArch64TargetParser.def b/include/llvm/Support/AArch64TargetParser.def index fd21e3615b7..e152f383b3e 100644 --- a/include/llvm/Support/AArch64TargetParser.def +++ b/include/llvm/Support/AArch64TargetParser.def @@ -79,7 +79,6 @@ AARCH64_ARCH_EXT_NAME("memtag", AArch64::AEK_MTE, "+mte", "-mte") AARCH64_ARCH_EXT_NAME("ssbs", AArch64::AEK_SSBS, "+ssbs", "-ssbs") AARCH64_ARCH_EXT_NAME("sb", AArch64::AEK_SB, "+sb", "-sb") AARCH64_ARCH_EXT_NAME("predres", AArch64::AEK_PREDRES, "+predres", "-predres") -AARCH64_ARCH_EXT_NAME("tme", AArch64::AEK_TME, "+tme", "-tme") #undef AARCH64_ARCH_EXT_NAME #ifndef AARCH64_CPU_NAME diff --git a/include/llvm/Support/AArch64TargetParser.h b/include/llvm/Support/AArch64TargetParser.h index 564f831b070..965d38535e7 100644 --- a/include/llvm/Support/AArch64TargetParser.h +++ b/include/llvm/Support/AArch64TargetParser.h @@ -54,7 +54,6 @@ enum ArchExtKind : unsigned { AEK_SVE2SM4 = 1 << 25, AEK_SVE2SHA3 = 1 << 26, AEK_BITPERM = 1 << 27, - AEK_TME = 1 << 28, }; enum class ArchKind { diff --git a/lib/Target/AArch64/AArch64.td b/lib/Target/AArch64/AArch64.td index fcd5818727f..e39c6995e36 100644 --- a/lib/Target/AArch64/AArch64.td +++ b/lib/Target/AArch64/AArch64.td @@ -345,9 +345,6 @@ def FeatureRandGen : SubtargetFeature<"rand", "HasRandGen", def FeatureMTE : SubtargetFeature<"mte", "HasMTE", "true", "Enable Memory Tagging Extension" >; -def FeatureTME : SubtargetFeature<"tme", "HasTME", - "true", "Enable Transactional Memory Extension" >; - //===----------------------------------------------------------------------===// // Architectures. // diff --git a/lib/Target/AArch64/AArch64InstrFormats.td b/lib/Target/AArch64/AArch64InstrFormats.td index 2af5726fc4f..74fa5ef713d 100644 --- a/lib/Target/AArch64/AArch64InstrFormats.td +++ b/lib/Target/AArch64/AArch64InstrFormats.td @@ -714,15 +714,12 @@ def logical_imm64_not : Operand { let ParserMatchClass = LogicalImm64NotOperand; } -// iXX_imm0_65535 predicates - True if the immediate is in the range [0,65535]. -let ParserMatchClass = AsmImmRange<0, 65535>, PrintMethod = "printImmHex" in { -def i32_imm0_65535 : Operand, ImmLeaf, ImmLeaf; - -def i64_imm0_65535 : Operand, ImmLeaf; +}]> { + let ParserMatchClass = AsmImmRange<0, 65535>; + let PrintMethod = "printImmHex"; } // imm0_255 predicate - True if the immediate is in the range [0,255]. @@ -1085,46 +1082,6 @@ class RtSystemI let Inst{4-0} = Rt; } -// System instructions for transactional memory extension -class TMBaseSystemI CRm, bits<3> op2, dag oops, dag iops, - string asm, string operands, list pattern> - : BaseSystemI, - Sched<[WriteSys]> { - let Inst{20-12} = 0b000110011; - let Inst{11-8} = CRm; - let Inst{7-5} = op2; - let DecoderMethod = ""; - - let mayLoad = 1; - let mayStore = 1; -} - -// System instructions for transactional memory - single input operand -class TMSystemI CRm, string asm, list pattern> - : TMBaseSystemI<0b1, CRm, 0b011, - (outs GPR64:$Rt), (ins), asm, "\t$Rt", pattern> { - bits<5> Rt; - let Inst{4-0} = Rt; -} - -// System instructions for transactional memory - no operand -class TMSystemINoOperand CRm, string asm, list pattern> - : TMBaseSystemI<0b0, CRm, 0b011, (outs), (ins), asm, "", pattern> { - let Inst{4-0} = 0b11111; -} - -// System instructions for exit from transactions -let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in -class TMSystemException op1, string asm, list pattern> - : I<(outs), (ins i64_imm0_65535:$imm), asm, "\t$imm", "", pattern>, - Sched<[WriteSys]> { - bits<16> imm; - let Inst{31-24} = 0b11010100; - let Inst{23-21} = op1; - let Inst{20-5} = imm; - let Inst{4-0} = 0b00000; -} - // Hint instructions that take both a CRm and a 3-bit immediate. // NOTE: ideally, this would have mayStore = 0, mayLoad = 0, but we cannot // model patterns with sufficiently fine granularity @@ -4129,7 +4086,7 @@ multiclass MemTagStore opc1, string insn> { let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in class ExceptionGeneration op1, bits<2> ll, string asm> - : I<(outs), (ins i32_imm0_65535:$imm), asm, "\t$imm", "", []>, + : I<(outs), (ins imm0_65535:$imm), asm, "\t$imm", "", []>, Sched<[WriteSys]> { bits<16> imm; let Inst{31-24} = 0b11010100; diff --git a/lib/Target/AArch64/AArch64InstrInfo.td b/lib/Target/AArch64/AArch64InstrInfo.td index 74f07f569a5..897b3ebb384 100644 --- a/lib/Target/AArch64/AArch64InstrInfo.td +++ b/lib/Target/AArch64/AArch64InstrInfo.td @@ -133,8 +133,6 @@ def HasBTI : Predicate<"Subtarget->hasBTI()">, AssemblerPredicate<"FeatureBranchTargetId", "bti">; def HasMTE : Predicate<"Subtarget->hasMTE()">, AssemblerPredicate<"FeatureMTE", "mte">; -def HasTME : Predicate<"Subtarget->hasTME()">, - AssemblerPredicate<"FeatureTME", "tme">; def IsLE : Predicate<"Subtarget->isLittleEndian()">; def IsBE : Predicate<"!Subtarget->isLittleEndian()">; def IsWindows : Predicate<"Subtarget->isTargetWindows()">; @@ -800,21 +798,6 @@ def : InstAlias<"sys $op1, $Cn, $Cm, $op2", (SYSxt imm0_7:$op1, sys_cr_op:$Cn, sys_cr_op:$Cm, imm0_7:$op2, XZR)>; - -let Predicates = [HasTME] in { - -def TSTART : TMSystemI<0b0000, "tstart", [(set GPR64:$Rt, (int_aarch64_tstart))]>; - -def TCOMMIT : TMSystemINoOperand<0b0000, "tcommit", [(int_aarch64_tcommit)]>; - -let mayLoad = 0, mayStore = 0 in { -def TTEST : TMSystemI<0b0001, "ttest", [(set GPR64:$Rt, (int_aarch64_ttest))]>; -def TCANCEL : TMSystemException<0b011, "tcancel", [(int_aarch64_tcancel i64_imm0_65535:$imm)]> { - let isBarrier = 1; -} -} -} // HasTME - //===----------------------------------------------------------------------===// // Move immediate instructions. //===----------------------------------------------------------------------===// @@ -826,12 +809,12 @@ let PostEncoderMethod = "fixMOVZ" in defm MOVZ : MoveImmediate<0b10, "movz">; // First group of aliases covers an implicit "lsl #0". -def : InstAlias<"movk $dst, $imm", (MOVKWi GPR32:$dst, i32_imm0_65535:$imm, 0), 0>; -def : InstAlias<"movk $dst, $imm", (MOVKXi GPR64:$dst, i32_imm0_65535:$imm, 0), 0>; -def : InstAlias<"movn $dst, $imm", (MOVNWi GPR32:$dst, i32_imm0_65535:$imm, 0)>; -def : InstAlias<"movn $dst, $imm", (MOVNXi GPR64:$dst, i32_imm0_65535:$imm, 0)>; -def : InstAlias<"movz $dst, $imm", (MOVZWi GPR32:$dst, i32_imm0_65535:$imm, 0)>; -def : InstAlias<"movz $dst, $imm", (MOVZXi GPR64:$dst, i32_imm0_65535:$imm, 0)>; +def : InstAlias<"movk $dst, $imm", (MOVKWi GPR32:$dst, imm0_65535:$imm, 0), 0>; +def : InstAlias<"movk $dst, $imm", (MOVKXi GPR64:$dst, imm0_65535:$imm, 0), 0>; +def : InstAlias<"movn $dst, $imm", (MOVNWi GPR32:$dst, imm0_65535:$imm, 0)>; +def : InstAlias<"movn $dst, $imm", (MOVNXi GPR64:$dst, imm0_65535:$imm, 0)>; +def : InstAlias<"movz $dst, $imm", (MOVZWi GPR32:$dst, imm0_65535:$imm, 0)>; +def : InstAlias<"movz $dst, $imm", (MOVZXi GPR64:$dst, imm0_65535:$imm, 0)>; // Next, we have various ELF relocations with the ":XYZ_g0:sym" syntax. def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g3:$sym, 48)>; diff --git a/lib/Target/AArch64/AArch64Subtarget.h b/lib/Target/AArch64/AArch64Subtarget.h index ce829795309..0c84cfb8329 100644 --- a/lib/Target/AArch64/AArch64Subtarget.h +++ b/lib/Target/AArch64/AArch64Subtarget.h @@ -134,7 +134,6 @@ protected: bool HasBTI = false; bool HasRandGen = false; bool HasMTE = false; - bool HasTME = false; // Arm SVE2 extensions bool HasSVE2AES = false; @@ -381,7 +380,6 @@ public: bool hasBTI() const { return HasBTI; } bool hasRandGen() const { return HasRandGen; } bool hasMTE() const { return HasMTE; } - bool hasTME() const { return HasTME; } // Arm SVE2 extensions bool hasSVE2AES() const { return HasSVE2AES; } bool hasSVE2SM4() const { return HasSVE2SM4; } diff --git a/test/CodeGen/AArch64/tme-tcancel.ll b/test/CodeGen/AArch64/tme-tcancel.ll deleted file mode 100644 index f4fb7b665de..00000000000 --- a/test/CodeGen/AArch64/tme-tcancel.ll +++ /dev/null @@ -1,16 +0,0 @@ -; RUN: llc %s -o - | FileCheck %s - -target triple = "aarch64-unknown-unknown-eabi" - -define void @test_tcancel() #0 { - tail call void @llvm.aarch64.tcancel(i64 0) #1 - unreachable -} - -declare void @llvm.aarch64.tcancel(i64 immarg) #1 - -attributes #0 = { "target-features"="+tme" } -attributes #1 = { nounwind noreturn } - -; CHECK-LABEL: test_tcancel -; CHECK: tcancel diff --git a/test/CodeGen/AArch64/tme-tcommit.ll b/test/CodeGen/AArch64/tme-tcommit.ll deleted file mode 100644 index cd85a3e5bd8..00000000000 --- a/test/CodeGen/AArch64/tme-tcommit.ll +++ /dev/null @@ -1,16 +0,0 @@ -; RUN: llc %s -o - | FileCheck %s - -target triple = "aarch64-unknown-unknown-eabi" - -define void @test_tcommit() #0 { - tail call void @llvm.aarch64.tcommit() - ret void -} - -declare void @llvm.aarch64.tcommit() #1 - -attributes #0 = { "target-features"="+tme" } -attributes #1 = { nounwind } - -; CHECK-LABEL: test_tcommit -; CHECK: tcommit diff --git a/test/CodeGen/AArch64/tme-tstart.ll b/test/CodeGen/AArch64/tme-tstart.ll deleted file mode 100644 index c761842e798..00000000000 --- a/test/CodeGen/AArch64/tme-tstart.ll +++ /dev/null @@ -1,16 +0,0 @@ -; RUN: llc %s -o - | FileCheck %s - -target triple = "aarch64-unknown-unknown-eabi" - -define i64 @test_tstart() #0 { - %r = tail call i64 @llvm.aarch64.tstart() - ret i64 %r -} - -declare i64 @llvm.aarch64.tstart() #1 - -attributes #0 = { "target-features"="+tme" } -attributes #1 = { nounwind } - -; CHECK-LABEL: test_tstart -; CHECK: tstart x diff --git a/test/CodeGen/AArch64/tme-ttest.ll b/test/CodeGen/AArch64/tme-ttest.ll deleted file mode 100644 index 59782108135..00000000000 --- a/test/CodeGen/AArch64/tme-ttest.ll +++ /dev/null @@ -1,16 +0,0 @@ -; RUN: llc %s -o - | FileCheck %s - -target triple = "aarch64-unknown-unknown-eabi" - -define i64 @test_ttest() #0 { - %r = tail call i64 @llvm.aarch64.ttest() - ret i64 %r -} - -declare i64 @llvm.aarch64.ttest() #1 - -attributes #0 = { "target-features"="+tme" } -attributes #1 = { nounwind } - -; CHECK-LABEL: test_ttest -; CHECK: ttest x diff --git a/test/MC/AArch64/tme-error.s b/test/MC/AArch64/tme-error.s deleted file mode 100644 index f91f58fa3ef..00000000000 --- a/test/MC/AArch64/tme-error.s +++ /dev/null @@ -1,47 +0,0 @@ -// Tests for transactional memory extension instructions -// RUN: not llvm-mc -triple aarch64 -show-encoding -mattr=+tme < %s 2>&1 | FileCheck %s - -tstart -// CHECK: error: too few operands for instruction -// CHECK-NEXT: tstart -tstart x4, x5 -// CHECK: error: invalid operand for instruction -// CHECK-NEXT: tstart x4, x5 -tstart x4, #1 -// CHECK: error: invalid operand for instruction -// CHECK-NEXT: tstart x4, #1 -tstart sp -// CHECK: error: invalid operand for instruction -// CHECK-NEXT: tstart sp - -ttest -// CHECK: error: too few operands for instruction -// CHECK-NEXT: ttest -ttest x4, x5 -// CHECK: error: invalid operand for instruction -// CHECK-NEXT: ttest x4, x5 -ttest x4, #1 -// CHECK: error: invalid operand for instruction -// CHECK-NEXT: ttest x4, #1 -ttest sp -// CHECK: error: invalid operand for instruction -// CHECK-NEXT: ttest sp - -tcommit x4 -// CHECK: error: invalid operand for instruction -// CHECK-NEXT: tcommit x4 -tcommit sp -// CHECK: error: invalid operand for instruction -// CHECK-NEXT: tcommit sp - - -tcancel -// CHECK: error: too few operands for instruction -// CHECK-NEXT tcancel -tcancel x0 -// CHECK: error: immediate must be an integer in range [0, 65535] -// CHECK-NEXT tcancel -tcancel #65536 -// CHECK: error: immediate must be an integer in range [0, 65535] -// CHECK-NEXT: tcancel #65536 - diff --git a/test/MC/AArch64/tme.s b/test/MC/AArch64/tme.s deleted file mode 100644 index cd472741276..00000000000 --- a/test/MC/AArch64/tme.s +++ /dev/null @@ -1,24 +0,0 @@ -// Tests for transaction memory extension instructions -// -// RUN: llvm-mc -triple aarch64 -show-encoding -mattr=+tme < %s | FileCheck %s -// RUN: not llvm-mc -triple aarch64 -show-encoding -mattr=-tme < %s 2>&1 | FileCheck %s --check-prefix=NOTME - -tstart x3 -ttest x4 -tcommit -tcancel #0x1234 - -// CHECK: tstart x3 // encoding: [0x63,0x30,0x23,0xd5] -// CHECK: ttest x4 // encoding: [0x64,0x31,0x23,0xd5] -// CHECK: tcommit // encoding: [0x7f,0x30,0x03,0xd5] -// CHECK: tcancel #0x1234 // encoding: [0x80,0x46,0x62,0xd4] - - -// NOTME: instruction requires: tme -// NOTME-NEXT: tstart x3 -// NOTME: instruction requires: tme -// NOTME-NEXT: ttest x4 -// NOTME: instruction requires: tme -// NOTME-NEXT: tcommit -// NOTME: instruction requires: tme -// NOTME-NEXT: tcancel #0x1234 diff --git a/test/MC/Disassembler/AArch64/tme.txt b/test/MC/Disassembler/AArch64/tme.txt deleted file mode 100644 index f250b33e0e1..00000000000 --- a/test/MC/Disassembler/AArch64/tme.txt +++ /dev/null @@ -1,19 +0,0 @@ -# Tests for transaction memory extension instructions -# RUN: llvm-mc -triple=aarch64 -mattr=+tme -disassemble < %s | FileCheck %s -# RUN: not llvm-mc -triple=aarch64 -mattr=-tme -disassemble < %s 2>&1 | FileCheck %s --check-prefix=NOTME - -[0x63,0x30,0x23,0xd5] -[0x64,0x31,0x23,0xd5] -[0x7f,0x30,0x03,0xd5] -[0x80,0x46,0x62,0xd4] - -# CHECK: tstart x3 -# CHECK: ttest x4 -# CHECK: tcommit -# CHECK: tcancel #0x1234 - -# NOTEME: mrs -# NOTEME-NEXT: mrs -# NOTEME-NEXT: msr -# NOTME: warning: invalid instruction encoding -# NOTME-NEXT: [0x80,0x46,0x62,0xd4] diff --git a/unittests/Support/TargetParserTest.cpp b/unittests/Support/TargetParserTest.cpp index 5ef8f2e4b55..34c7a8a4fd1 100644 --- a/unittests/Support/TargetParserTest.cpp +++ b/unittests/Support/TargetParserTest.cpp @@ -1119,7 +1119,6 @@ TEST(TargetParserTest, AArch64ArchExtFeature) { {"rcpc", "norcpc", "+rcpc", "-rcpc" }, {"rng", "norng", "+rand", "-rand"}, {"memtag", "nomemtag", "+mte", "-mte"}, - {"tme", "notme", "+tme", "-tme"}, {"ssbs", "nossbs", "+ssbs", "-ssbs"}, {"sb", "nosb", "+sb", "-sb"}, {"predres", "nopredres", "+predres", "-predres"} -- 2.40.0