From 7fc61c0367b94624214a42d93b8fcf40927f042e Mon Sep 17 00:00:00 2001
From: Simon Tatham <simon.tatham@arm.com>
Date: Mon, 10 Jun 2019 14:43:55 +0000
Subject: [PATCH] [ARM] Disallow PC, and optionally SP, in VMOVRH and VMOVHR.

Arm v8.1-M supports the VMOV instructions that move a half-precision
value to and from a GPR, but not if the GPR is SP or PC.

To fix this, I've changed those instructions to use the rGPR register
class instead of GPR. rGPR always excludes PC, and it excludes SP
except in the presence of the HasV8Ops target feature (i.e. Arm v8-A).
So the effect is that VMOV.F16 to and from PC is now illegal
everywhere, but VMOV.F16 to and from SP is illegal only on non-v8-A
cores (which I believe is all as it should be).

Reviewers: dmgreen, samparker, SjoerdMeijer, ostannard

Reviewed By: ostannard

Subscribers: ostannard, javed.absar, kristof.beyls, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D60704


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362942 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/ARM/ARMInstrVFP.td |  8 ++++----
 test/MC/ARM/vmovhr.s          | 24 ++++++++++++++++++++++++
 2 files changed, 28 insertions(+), 4 deletions(-)
 create mode 100644 test/MC/ARM/vmovhr.s

diff --git a/lib/Target/ARM/ARMInstrVFP.td b/lib/Target/ARM/ARMInstrVFP.td
index 6f042d39a4c..6498024869a 100644
--- a/lib/Target/ARM/ARMInstrVFP.td
+++ b/lib/Target/ARM/ARMInstrVFP.td
@@ -1246,9 +1246,9 @@ def VMOVSRR : AVConv5I<0b11000100, 0b1010,
 
 // Move H->R, clearing top 16 bits
 def VMOVRH : AVConv2I<0b11100001, 0b1001,
-                      (outs GPR:$Rt), (ins HPR:$Sn),
+                      (outs rGPR:$Rt), (ins HPR:$Sn),
                       IIC_fpMOVSI, "vmov", ".f16\t$Rt, $Sn",
-                      [(set GPR:$Rt, (arm_vmovrh HPR:$Sn))]>,
+                      [(set rGPR:$Rt, (arm_vmovrh HPR:$Sn))]>,
              Requires<[HasFPRegs16]>,
              Sched<[WriteFPMOV]> {
   // Instruction operands.
@@ -1268,9 +1268,9 @@ def VMOVRH : AVConv2I<0b11100001, 0b1001,
 
 // Move R->H, clearing top 16 bits
 def VMOVHR : AVConv4I<0b11100000, 0b1001,
-                      (outs HPR:$Sn), (ins GPR:$Rt),
+                      (outs HPR:$Sn), (ins rGPR:$Rt),
                       IIC_fpMOVIS, "vmov", ".f16\t$Sn, $Rt",
-                      [(set HPR:$Sn, (arm_vmovhr GPR:$Rt))]>,
+                      [(set HPR:$Sn, (arm_vmovhr rGPR:$Rt))]>,
              Requires<[HasFPRegs16]>,
              Sched<[WriteFPMOV]> {
   // Instruction operands.
diff --git a/test/MC/ARM/vmovhr.s b/test/MC/ARM/vmovhr.s
new file mode 100644
index 00000000000..608400d5215
--- /dev/null
+++ b/test/MC/ARM/vmovhr.s
@@ -0,0 +1,24 @@
+// RUN: not llvm-mc -triple=thumbv8.2a-none-eabi -mattr=+fp-armv8,+fullfp16 -show-encoding < %s 2>%t \
+// RUN:   | FileCheck %s
+// RUN:     FileCheck --check-prefix=ERROR < %t %s
+
+# CHECK: vmov.f16 r0, s13 @ encoding: [0x16,0xee,0x90,0x09]
+vmov.f16 r0, s13
+
+# CHECK: vmov.f16 s21, r1 @ encoding: [0x0a,0xee,0x90,0x19]
+vmov.f16 s21, r1
+
+# CHECK: vmov.f16 s2, sp @ encoding: [0x01,0xee,0x10,0xd9]
+vmov.f16 s2, sp
+
+# ERROR: :[[@LINE+2]]:{{[0-9]+}}: error: invalid instruction
+# ERROR: operand must be a register in range [r0, r14]
+vmov.f16 s3, pc
+
+# CHECK: vmov.f16 sp, s5 @ encoding: [0x12,0xee,0x90,0xd9]
+vmov.f16 sp, s5
+
+# ERROR: :[[@LINE+2]]:{{[0-9]+}}: error: invalid instruction
+# ERROR: operand must be a register in range [r0, r14]
+vmov.f16 pc, s8
+
-- 
2.40.0