From 7d4e49b75c2d2a465baae50dc1b04f973d255f0c Mon Sep 17 00:00:00 2001 From: Alex Bradbury Date: Mon, 15 Jan 2018 20:45:15 +0000 Subject: [PATCH] [RISCV] Fix test failures on non-assert builds introduced in r322494 Thanks to Eli Friedman, who suggested the reason these tests failed on a few buildbots yet works fine locally is because non-assert builds don't emit value labels. git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@322514 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/CodeGen/riscv32-abi.c | 9 +++------ test/CodeGen/riscv64-abi.c | 9 +++------ 2 files changed, 6 insertions(+), 12 deletions(-) diff --git a/test/CodeGen/riscv32-abi.c b/test/CodeGen/riscv32-abi.c index e32a8c258f..d83a8f5d74 100644 --- a/test/CodeGen/riscv32-abi.c +++ b/test/CodeGen/riscv32-abi.c @@ -269,8 +269,7 @@ int f_va_1(char *fmt, ...) { // correct offsets are used. // CHECK-LABEL: @f_va_2( -// CHECK-NEXT: entry: -// CHECK-NEXT: [[FMT_ADDR:%.*]] = alloca i8*, align 4 +// CHECK: [[FMT_ADDR:%.*]] = alloca i8*, align 4 // CHECK-NEXT: [[VA:%.*]] = alloca i8*, align 4 // CHECK-NEXT: [[V:%.*]] = alloca double, align 8 // CHECK-NEXT: store i8* [[FMT:%.*]], i8** [[FMT_ADDR]], align 4 @@ -303,8 +302,7 @@ double f_va_2(char *fmt, ...) { // Two "aligned" register pairs. // CHECK-LABEL: @f_va_3( -// CHECK-NEXT: entry: -// CHECK-NEXT: [[FMT_ADDR:%.*]] = alloca i8*, align 4 +// CHECK: [[FMT_ADDR:%.*]] = alloca i8*, align 4 // CHECK-NEXT: [[VA:%.*]] = alloca i8*, align 4 // CHECK-NEXT: [[V:%.*]] = alloca double, align 8 // CHECK-NEXT: [[W:%.*]] = alloca i32, align 4 @@ -357,8 +355,7 @@ double f_va_3(char *fmt, ...) { } // CHECK-LABEL: define i32 @f_va_4(i8* %fmt, ...) {{.*}} { -// CHECK-NEXT: entry: -// CHECK-NEXT: [[FMT_ADDR:%.*]] = alloca i8*, align 4 +// CHECK: [[FMT_ADDR:%.*]] = alloca i8*, align 4 // CHECK-NEXT: [[VA:%.*]] = alloca i8*, align 4 // CHECK-NEXT: [[V:%.*]] = alloca i32, align 4 // CHECK-NEXT: [[LD:%.*]] = alloca fp128, align 16 diff --git a/test/CodeGen/riscv64-abi.c b/test/CodeGen/riscv64-abi.c index 90bc54f071..321c0e3df3 100644 --- a/test/CodeGen/riscv64-abi.c +++ b/test/CodeGen/riscv64-abi.c @@ -267,8 +267,7 @@ int f_va_1(char *fmt, ...) { // correct offsets are used. // CHECK-LABEL: @f_va_2( -// CHECK-NEXT: entry: -// CHECK-NEXT: [[FMT_ADDR:%.*]] = alloca i8*, align 8 +// CHECK: [[FMT_ADDR:%.*]] = alloca i8*, align 8 // CHECK-NEXT: [[VA:%.*]] = alloca i8*, align 8 // CHECK-NEXT: [[V:%.*]] = alloca fp128, align 16 // CHECK-NEXT: store i8* [[FMT:%.*]], i8** [[FMT_ADDR]], align 8 @@ -301,8 +300,7 @@ long double f_va_2(char *fmt, ...) { // Two "aligned" register pairs. // CHECK-LABEL: @f_va_3( -// CHECK-NEXT: entry: -// CHECK-NEXT: [[FMT_ADDR:%.*]] = alloca i8*, align 8 +// CHECK: [[FMT_ADDR:%.*]] = alloca i8*, align 8 // CHECK-NEXT: [[VA:%.*]] = alloca i8*, align 8 // CHECK-NEXT: [[V:%.*]] = alloca fp128, align 16 // CHECK-NEXT: [[W:%.*]] = alloca i32, align 4 @@ -355,8 +353,7 @@ long double f_va_3(char *fmt, ...) { } // CHECK-LABEL: @f_va_4( -// CHECK-NEXT: entry: -// CHECK-NEXT: [[FMT_ADDR:%.*]] = alloca i8*, align 8 +// CHECK: [[FMT_ADDR:%.*]] = alloca i8*, align 8 // CHECK-NEXT: [[VA:%.*]] = alloca i8*, align 8 // CHECK-NEXT: [[V:%.*]] = alloca i32, align 4 // CHECK-NEXT: [[TS:%.*]] = alloca [[STRUCT_TINY:%.*]], align 2 -- 2.50.1