From 7a59801a26fbe314ba24765bbe7304672b4b445c Mon Sep 17 00:00:00 2001 From: Simon Atanasyan Date: Wed, 3 Jul 2019 10:33:16 +0000 Subject: [PATCH] [mips] Add SIGRIE,GINVI,GINVT to general scheduling definitions git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365023 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/MipsScheduleGeneric.td | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/lib/Target/Mips/MipsScheduleGeneric.td b/lib/Target/Mips/MipsScheduleGeneric.td index 4f3afeb720d..2729745c025 100644 --- a/lib/Target/Mips/MipsScheduleGeneric.td +++ b/lib/Target/Mips/MipsScheduleGeneric.td @@ -311,7 +311,7 @@ def : InstRW<[GenericWriteJumpAndLink], (instrs BALC, BEQZALC, BGEZALC, def : InstRW<[GenericWriteJump], (instrs BC, BC2EQZ, BC2NEZ, BEQC, BEQZC, BGEC, BGEUC, BGEZC, BGTZC, BLEZC, BLTC, BLTUC, BLTZC, BNEC, BNEZC, BNVC, BOVC, JIC, JR_HB_R6, - PseudoIndirectBranchR6, + SIGRIE, PseudoIndirectBranchR6, PseudoIndrectHazardBranchR6)>; def : InstRW<[GenericWriteJump], (instrs TAILCALLR6REG, TAILCALLHBR6REG)>; @@ -377,7 +377,7 @@ def : InstRW<[GenericWriteJump], (instrs BC16_MMR6, BC1EQZC_MMR6, BC1NEZC_MMR6, BNEZC16_MMR6, BNEZC_MMR6, BNVC_MMR6, BOVC_MMR6, DERET_MMR6, ERETNC_MMR6, ERET_MMR6, JIC_MMR6, JRADDIUSP, JRC16_MM, - JRC16_MMR6, JRCADDIUSP_MMR6, + JRC16_MMR6, JRCADDIUSP_MMR6, SIGRIE_MMR6, PseudoIndirectBranch_MMR6)>; def : InstRW<[GenericWriteJumpAndLink], (instrs BALC_MMR6, BEQZALC_MMR6, @@ -589,6 +589,8 @@ def : InstRW<[GenericWritePref], (instrs PREF_R6)>; def : InstRW<[GenericWriteCache], (instrs CACHE_R6)>; +def : InstRW<[GenericWriteSync], (instrs GINVI, GINVT)>; + // MIPS32 EVA // ========== @@ -649,6 +651,7 @@ def : InstRW<[GenericWritePref], (instrs PREF_MM, PREFX_MM)>; def : InstRW<[GenericWriteCache], (instrs CACHE_MM)>; def : InstRW<[GenericWriteSync], (instrs SYNC_MM, SYNCI_MM)>; +def : InstRW<[GenericWriteSync], (instrs GINVI_MMR6, GINVT_MMR6)>; // microMIPS32r6 // ============= -- 2.50.1