From 7a457502338f3217336852446ba068408222202c Mon Sep 17 00:00:00 2001 From: Tim Shen Date: Thu, 25 May 2017 22:58:35 +0000 Subject: [PATCH] [PPC] Fix atomics lowering in DAG lowering. I forgot to forward the chain, causing some missing instruction dependencies. The test crashes the compiler without this patch. Inspired by the test case, D33519 also tries to remove the extra sync. Differential Revision: https://reviews.llvm.org/D33573 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303931 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/PowerPC/PPCISelLowering.cpp | 4 +++- test/CodeGen/PowerPC/atomics-constant.ll | 23 +++++++++++++++++++++++ 2 files changed, 26 insertions(+), 1 deletion(-) create mode 100644 test/CodeGen/PowerPC/atomics-constant.ll diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp index 2f64a3f4eb5..7fde1238640 100644 --- a/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/lib/Target/PowerPC/PPCISelLowering.cpp @@ -8296,10 +8296,12 @@ SDValue PPCTargetLowering::LowerINTRINSIC_VOID(SDValue Op, SDLoc DL(Op); switch (cast(Op.getOperand(ArgStart))->getZExtValue()) { case Intrinsic::ppc_cfence: { + assert(ArgStart == 1); assert(Subtarget.isPPC64() && "Only 64-bit is supported for now."); return SDValue(DAG.getMachineNode(PPC::CFENCE8, DL, MVT::Other, DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, - Op.getOperand(ArgStart + 1))), + Op.getOperand(ArgStart + 1)), + Op.getOperand(0)), 0); } default: diff --git a/test/CodeGen/PowerPC/atomics-constant.ll b/test/CodeGen/PowerPC/atomics-constant.ll new file mode 100644 index 00000000000..a92ca813af8 --- /dev/null +++ b/test/CodeGen/PowerPC/atomics-constant.ll @@ -0,0 +1,23 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s | FileCheck %s + +target triple = "powerpc64le-unknown-linux-gnu" + +@a = constant i64 zeroinitializer + +define i64 @foo() { +; CHECK-LABEL: foo: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: addis 3, 2, .LC0@toc@ha +; CHECK-NEXT: li 4, 0 +; CHECK-NEXT: ld 3, .LC0@toc@l(3) +; CHECK-NEXT: cmpw 7, 4, 4 +; CHECK-NEXT: ld 3, 0(3) +; CHECK-NEXT: bne- 7, .+4 +; CHECK-NEXT: isync +; CHECK-NEXT: li 3, 0 +; CHECK-NEXT: blr +entry: + %value = load atomic i64, i64* @a acquire, align 8 + ret i64 %value +} -- 2.40.0