From 7930d75dbb4ea996131fc5792f72303cbeb69473 Mon Sep 17 00:00:00 2001 From: Krzysztof Parzyszek Date: Sat, 5 Nov 2016 21:02:54 +0000 Subject: [PATCH] [Hexagon] Round 1 of selection pattern simplifications Consistently use register class pat frags instead of spelling out the type and class each time. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286048 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Hexagon/HexagonPatterns.td | 534 +++++++++++++------------- 1 file changed, 267 insertions(+), 267 deletions(-) diff --git a/lib/Target/Hexagon/HexagonPatterns.td b/lib/Target/Hexagon/HexagonPatterns.td index 2dfe1570ab0..fe702a4ef5b 100644 --- a/lib/Target/Hexagon/HexagonPatterns.td +++ b/lib/Target/Hexagon/HexagonPatterns.td @@ -48,7 +48,7 @@ def DEC_CONST_UNSIGNED : SDNodeXForm; class T_CMP_pat - : Pat<(i1 (OpNode (i32 IntRegs:$src1), ImmPred:$src2)), + : Pat<(i1 (OpNode I32:$src1, ImmPred:$src2)), (MI IntRegs:$src1, ImmPred:$src2)>; def : T_CMP_pat ; @@ -63,7 +63,7 @@ def HexagonPACKHL : SDNode<"HexagonISD::PACKHL", SDTHexagonI64I32I32>; // Pats for instruction selection. class BinOp32_pat - : Pat<(ResT (Op (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))), + : Pat<(ResT (Op I32:$Rs, I32:$Rt)), (ResT (MI IntRegs:$Rs, IntRegs:$Rt))>; def: BinOp32_pat; @@ -82,7 +82,7 @@ class RevCmp : PatFrag<(ops node:$rhs, node:$lhs), F.Fragment>; // Pats for compares. They use PatFrags as operands, not SDNodes, // since seteq/setgt/etc. are defined as ParFrags. class T_cmp32_rr_pat - : Pat<(VT (Op (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))), + : Pat<(VT (Op I32:$Rs, I32:$Rt)), (VT (MI IntRegs:$Rs, IntRegs:$Rt))>; def: T_cmp32_rr_pat; @@ -92,22 +92,22 @@ def: T_cmp32_rr_pat; def: T_cmp32_rr_pat, i1>; def: T_cmp32_rr_pat, i1>; -def: Pat<(i32 (select (i1 PredRegs:$Pu), (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))), +def: Pat<(i32 (select I1:$Pu, I32:$Rs, I32:$Rt)), (C2_mux PredRegs:$Pu, IntRegs:$Rs, IntRegs:$Rt)>; def: Pat<(i32 (add I32:$Rs, s32_0ImmPred:$s16)), (i32 (A2_addi I32:$Rs, imm:$s16))>; -def: Pat<(or (i32 IntRegs:$Rs), s32_0ImmPred:$s10), +def: Pat<(or I32:$Rs, s32_0ImmPred:$s10), (A2_orir IntRegs:$Rs, imm:$s10)>; -def: Pat<(and (i32 IntRegs:$Rs), s32_0ImmPred:$s10), +def: Pat<(and I32:$Rs, s32_0ImmPred:$s10), (A2_andir IntRegs:$Rs, imm:$s10)>; def: Pat<(sub s32_0ImmPred:$s10, IntRegs:$Rs), (A2_subri imm:$s10, IntRegs:$Rs)>; // Rd = not(Rs) gets mapped to Rd=sub(#-1, Rs). -def: Pat<(not (i32 IntRegs:$src1)), +def: Pat<(not I32:$src1), (A2_subri -1, IntRegs:$src1)>; def: Pat<(s32_0ImmPred:$s16), (A2_tfrsi imm:$s16)>; @@ -204,7 +204,7 @@ let AddedComplexity = 200 in { } class T_cmp64_rr_pat - : Pat<(i1 (CmpOp (i64 DoubleRegs:$Rs), (i64 DoubleRegs:$Rt))), + : Pat<(i1 (CmpOp I64:$Rs, I64:$Rt)), (i1 (MI DoubleRegs:$Rs, DoubleRegs:$Rt))>; def: T_cmp64_rr_pat; @@ -220,7 +220,7 @@ def: Pat<(i64 (and I64:$Rs, I64:$Rt)), (A2_andp I64:$Rs, I64:$Rt)>; def: Pat<(i64 (or I64:$Rs, I64:$Rt)), (A2_orp I64:$Rs, I64:$Rt)>; def: Pat<(i64 (xor I64:$Rs, I64:$Rt)), (A2_xorp I64:$Rs, I64:$Rt)>; -def: Pat<(i1 (not (i1 PredRegs:$Ps))), +def: Pat<(i1 (not I1:$Ps)), (C2_not PredRegs:$Ps)>; def: Pat<(i1 (and I1:$Ps, I1:$Pt)), (C2_and I1:$Ps, I1:$Pt)>; @@ -237,12 +237,12 @@ def: Pat<(br bb:$dst), (J2_jump brtarget:$dst)>; def: Pat<(retflag), (PS_jmpret (i32 R31))>; -def: Pat<(brcond (i1 PredRegs:$src1), bb:$offset), +def: Pat<(brcond I1:$src1, bb:$offset), (J2_jumpt PredRegs:$src1, bb:$offset)>; def: Pat<(eh_return), (EH_RETURN_JMPR (i32 R31))>; -def: Pat<(brind (i32 IntRegs:$dst)), +def: Pat<(brind I32:$dst), (J2_jumpr IntRegs:$dst)>; // Patterns to select load-indexed (i.e. load from base+offset). @@ -253,9 +253,9 @@ multiclass Loadx_pat; def: Pat<(VT (Load (orisadd (i32 AddrFI:$fi), ImmPred:$Off))), (VT (MI AddrFI:$fi, imm:$Off))>; - def: Pat<(VT (Load (add (i32 IntRegs:$Rs), ImmPred:$Off))), + def: Pat<(VT (Load (add I32:$Rs, ImmPred:$Off))), (VT (MI IntRegs:$Rs, imm:$Off))>; - def: Pat<(VT (Load (i32 IntRegs:$Rs))), (VT (MI IntRegs:$Rs, 0))>; + def: Pat<(VT (Load I32:$Rs)), (VT (MI IntRegs:$Rs, 0))>; } let AddedComplexity = 20 in { @@ -281,7 +281,7 @@ let AddedComplexity = 20 in { // the 32-bit value. Since the loaded value can only be 0 or 1, 0-v should // do the trick. let AddedComplexity = 20 in -def: Pat<(i32 (sextloadi1 (i32 IntRegs:$Rs))), +def: Pat<(i32 (sextloadi1 I32:$Rs)), (A2_subri 0, (L2_loadrub_io IntRegs:$Rs, 0))>; def: Pat<(i32 (mul I32:$src1, I32:$src2)), (M2_mpyi I32:$src1, I32:$src2)>; @@ -410,13 +410,13 @@ multiclass Storex_fi_add_pat { - def: Pat<(Store Value:$Rt, (add (i32 IntRegs:$Rs), ImmPred:$Off)), + def: Pat<(Store Value:$Rt, (add I32:$Rs, ImmPred:$Off)), (MI IntRegs:$Rs, imm:$Off, Value:$Rt)>; - def: Pat<(Store Value:$Rt, (orisadd (i32 IntRegs:$Rs), ImmPred:$Off)), + def: Pat<(Store Value:$Rt, (orisadd I32:$Rs, ImmPred:$Off)), (MI IntRegs:$Rs, imm:$Off, Value:$Rt)>; } class Storex_simple_pat - : Pat<(Store Value:$Rt, (i32 IntRegs:$Rs)), + : Pat<(Store Value:$Rt, I32:$Rs), (MI IntRegs:$Rs, 0, Value:$Rt)>; // Patterns for generating stores, where the address takes different forms, @@ -435,14 +435,14 @@ multiclass Storexm_fi_add_pat { - def: Pat<(Store Value:$Rt, (add (i32 IntRegs:$Rs), ImmPred:$Off)), + def: Pat<(Store Value:$Rt, (add I32:$Rs, ImmPred:$Off)), (MI IntRegs:$Rs, imm:$Off, (ValueMod Value:$Rt))>; - def: Pat<(Store Value:$Rt, (orisadd (i32 IntRegs:$Rs), ImmPred:$Off)), + def: Pat<(Store Value:$Rt, (orisadd I32:$Rs, ImmPred:$Off)), (MI IntRegs:$Rs, imm:$Off, (ValueMod Value:$Rt))>; } class Storexm_simple_pat - : Pat<(Store Value:$Rt, (i32 IntRegs:$Rs)), + : Pat<(Store Value:$Rt, I32:$Rs), (MI IntRegs:$Rs, 0, (ValueMod Value:$Rt))>; multiclass Storex_pat; def: Pat <(i64 (sext I32:$src)), (A2_sxtw I32:$src)>; -def: Pat<(i32 (select (i1 (setlt (i32 IntRegs:$src), 0)), - (i32 (sub 0, (i32 IntRegs:$src))), - (i32 IntRegs:$src))), +def: Pat<(i32 (select (i1 (setlt I32:$src, 0)), + (i32 (sub 0, I32:$src)), + I32:$src)), (A2_abs IntRegs:$src)>; let AddedComplexity = 50 in -def: Pat<(i32 (xor (add (sra (i32 IntRegs:$src), (i32 31)), - (i32 IntRegs:$src)), - (sra (i32 IntRegs:$src), (i32 31)))), +def: Pat<(i32 (xor (add (sra I32:$src, (i32 31)), + I32:$src), + (sra I32:$src, (i32 31)))), (A2_abs IntRegs:$src)>; -def: Pat<(sra (i32 IntRegs:$src), u5_0ImmPred:$u5), +def: Pat<(sra I32:$src, u5_0ImmPred:$u5), (S2_asr_i_r IntRegs:$src, imm:$u5)>; -def: Pat<(srl (i32 IntRegs:$src), u5_0ImmPred:$u5), +def: Pat<(srl I32:$src, u5_0ImmPred:$u5), (S2_lsr_i_r IntRegs:$src, imm:$u5)>; -def: Pat<(shl (i32 IntRegs:$src), u5_0ImmPred:$u5), +def: Pat<(shl I32:$src, u5_0ImmPred:$u5), (S2_asl_i_r IntRegs:$src, imm:$u5)>; def: Pat<(i32 (sra (i32 (add (i32 (sra I32:$src1, u5_0ImmPred:$src2)), @@ -526,7 +526,7 @@ def: Pat<(i32 (sra (i32 (add (i32 (sra I32:$src1, u5_0ImmPred:$src2)), (i32 1))), (S2_asr_i_r_rnd IntRegs:$src1, u5_0ImmPred:$src2)>; -def : Pat<(not (i64 DoubleRegs:$src1)), +def : Pat<(not I64:$src1), (A2_notp DoubleRegs:$src1)>; // Count leading zeros. @@ -543,55 +543,55 @@ def: Pat<(i32 (trunc (ctlz (not I64:$Rss)))), (S2_cl1p I64:$Rss)>; // Count trailing ones: 32-bit. def: Pat<(i32 (cttz (not I32:$Rs))), (S2_ct1 I32:$Rs)>; -def: Pat<(i32 (and (i32 IntRegs:$Rs), (not (shl 1, u5_0ImmPred:$u5)))), +def: Pat<(i32 (and I32:$Rs, (not (shl 1, u5_0ImmPred:$u5)))), (S2_clrbit_i IntRegs:$Rs, u5_0ImmPred:$u5)>; -def: Pat<(i32 (or (i32 IntRegs:$Rs), (shl 1, u5_0ImmPred:$u5))), +def: Pat<(i32 (or I32:$Rs, (shl 1, u5_0ImmPred:$u5))), (S2_setbit_i IntRegs:$Rs, u5_0ImmPred:$u5)>; -def: Pat<(i32 (xor (i32 IntRegs:$Rs), (shl 1, u5_0ImmPred:$u5))), +def: Pat<(i32 (xor I32:$Rs, (shl 1, u5_0ImmPred:$u5))), (S2_togglebit_i IntRegs:$Rs, u5_0ImmPred:$u5)>; -def: Pat<(i32 (and (i32 IntRegs:$Rs), (not (shl 1, (i32 IntRegs:$Rt))))), +def: Pat<(i32 (and I32:$Rs, (not (shl 1, I32:$Rt)))), (S2_clrbit_r IntRegs:$Rs, IntRegs:$Rt)>; -def: Pat<(i32 (or (i32 IntRegs:$Rs), (shl 1, (i32 IntRegs:$Rt)))), +def: Pat<(i32 (or I32:$Rs, (shl 1, I32:$Rt))), (S2_setbit_r IntRegs:$Rs, IntRegs:$Rt)>; -def: Pat<(i32 (xor (i32 IntRegs:$Rs), (shl 1, (i32 IntRegs:$Rt)))), +def: Pat<(i32 (xor I32:$Rs, (shl 1, I32:$Rt))), (S2_togglebit_r IntRegs:$Rs, IntRegs:$Rt)>; let AddedComplexity = 20 in { // Complexity greater than cmp reg-imm. - def: Pat<(i1 (setne (and (shl 1, u5_0ImmPred:$u5), (i32 IntRegs:$Rs)), 0)), + def: Pat<(i1 (setne (and (shl 1, u5_0ImmPred:$u5), I32:$Rs), 0)), (S2_tstbit_i IntRegs:$Rs, u5_0ImmPred:$u5)>; - def: Pat<(i1 (setne (and (shl 1, (i32 IntRegs:$Rt)), (i32 IntRegs:$Rs)), 0)), + def: Pat<(i1 (setne (and (shl 1, I32:$Rt), I32:$Rs), 0)), (S2_tstbit_r IntRegs:$Rs, IntRegs:$Rt)>; - def: Pat<(i1 (trunc (i32 IntRegs:$Rs))), + def: Pat<(i1 (trunc I32:$Rs)), (S2_tstbit_i IntRegs:$Rs, 0)>; - def: Pat<(i1 (trunc (i64 DoubleRegs:$Rs))), + def: Pat<(i1 (trunc I64:$Rs)), (S2_tstbit_i (LoReg DoubleRegs:$Rs), 0)>; } let AddedComplexity = 20 in { // Complexity greater than compare reg-imm. - def: Pat<(i1 (seteq (and (i32 IntRegs:$Rs), u6_0ImmPred:$u6), 0)), + def: Pat<(i1 (seteq (and I32:$Rs, u6_0ImmPred:$u6), 0)), (C2_bitsclri IntRegs:$Rs, u6_0ImmPred:$u6)>; - def: Pat<(i1 (seteq (and (i32 IntRegs:$Rs), (i32 IntRegs:$Rt)), 0)), + def: Pat<(i1 (seteq (and I32:$Rs, I32:$Rt), 0)), (C2_bitsclr IntRegs:$Rs, IntRegs:$Rt)>; } let AddedComplexity = 10 in // Complexity greater than compare reg-reg. -def: Pat<(i1 (seteq (and (i32 IntRegs:$Rs), (i32 IntRegs:$Rt)), IntRegs:$Rt)), +def: Pat<(i1 (seteq (and I32:$Rs, I32:$Rt), IntRegs:$Rt)), (C2_bitsset IntRegs:$Rs, IntRegs:$Rt)>; -def: Pat<(or (or (shl (or (shl (i32 (extloadi8 (add (i32 IntRegs:$b), 3))), +def: Pat<(or (or (shl (or (shl (i32 (extloadi8 (add I32:$b, 3))), (i32 8)), - (i32 (zextloadi8 (add (i32 IntRegs:$b), 2)))), + (i32 (zextloadi8 (add I32:$b, 2)))), (i32 16)), - (shl (i32 (zextloadi8 (add (i32 IntRegs:$b), 1))), (i32 8))), - (zextloadi8 (i32 IntRegs:$b))), + (shl (i32 (zextloadi8 (add I32:$b, 1))), (i32 8))), + (zextloadi8 I32:$b)), (A2_swiz (L2_loadri_io IntRegs:$b, 0))>; // Patterns for loads of i1: def: Pat<(i1 (load AddrFI:$fi)), (C2_tfrrp (L2_loadrub_io AddrFI:$fi, 0))>; -def: Pat<(i1 (load (add (i32 IntRegs:$Rs), s32_0ImmPred:$Off))), +def: Pat<(i1 (load (add I32:$Rs, s32_0ImmPred:$Off))), (C2_tfrrp (L2_loadrub_io IntRegs:$Rs, imm:$Off))>; -def: Pat<(i1 (load (i32 IntRegs:$Rs))), +def: Pat<(i1 (load I32:$Rs)), (C2_tfrrp (L2_loadrub_io IntRegs:$Rs, 0))>; def I1toI32: OutPatFrag<(ops node:$Rs), @@ -603,15 +603,15 @@ def I32toI1: OutPatFrag<(ops node:$Rs), defm: Storexm_pat; def: Storexm_simple_pat; -def: Pat<(sra (i64 DoubleRegs:$src), u6_0ImmPred:$u6), +def: Pat<(sra I64:$src, u6_0ImmPred:$u6), (S2_asr_i_p DoubleRegs:$src, imm:$u6)>; -def: Pat<(srl (i64 DoubleRegs:$src), u6_0ImmPred:$u6), +def: Pat<(srl I64:$src, u6_0ImmPred:$u6), (S2_lsr_i_p DoubleRegs:$src, imm:$u6)>; -def: Pat<(shl (i64 DoubleRegs:$src), u6_0ImmPred:$u6), +def: Pat<(shl I64:$src, u6_0ImmPred:$u6), (S2_asl_i_p DoubleRegs:$src, imm:$u6)>; let AddedComplexity = 100 in -def: Pat<(add (i32 IntRegs:$Rt), (shl (i32 IntRegs:$Rs), u3_0ImmPred:$u3)), +def: Pat<(add I32:$Rt, (shl I32:$Rs, u3_0ImmPred:$u3)), (S2_addasl_rrri IntRegs:$Rt, IntRegs:$Rs, imm:$u3)>; def HexagonBARRIER: SDNode<"HexagonISD::BARRIER", SDTNone, [SDNPHasChain]>; @@ -670,76 +670,76 @@ def: Pat<(HexagonTCRet I32:$dst), (PS_tailcall_r I32:$dst)>; // Map from r0 = and(r1, 65535) to r0 = zxth(r1) -def: Pat<(and (i32 IntRegs:$src1), 65535), +def: Pat<(and I32:$src1, 65535), (A2_zxth IntRegs:$src1)>; // Map from r0 = and(r1, 255) to r0 = zxtb(r1). -def: Pat<(and (i32 IntRegs:$src1), 255), +def: Pat<(and I32:$src1, 255), (A2_zxtb IntRegs:$src1)>; // Map Add(p1, true) to p1 = not(p1). // Add(p1, false) should never be produced, // if it does, it got to be mapped to NOOP. -def: Pat<(add (i1 PredRegs:$src1), -1), +def: Pat<(add I1:$src1, -1), (C2_not PredRegs:$src1)>; // Map from p0 = pnot(p0); r0 = mux(p0, #i, #j) => r0 = mux(p0, #j, #i). -def: Pat<(select (not (i1 PredRegs:$src1)), s8_0ImmPred:$src2, s32_0ImmPred:$src3), +def: Pat<(select (not I1:$src1), s8_0ImmPred:$src2, s32_0ImmPred:$src3), (C2_muxii PredRegs:$src1, s32_0ImmPred:$src3, s8_0ImmPred:$src2)>; // Map from p0 = pnot(p0); r0 = select(p0, #i, r1) // => r0 = C2_muxir(p0, r1, #i) -def: Pat<(select (not (i1 PredRegs:$src1)), s32_0ImmPred:$src2, - (i32 IntRegs:$src3)), +def: Pat<(select (not I1:$src1), s32_0ImmPred:$src2, + I32:$src3), (C2_muxir PredRegs:$src1, IntRegs:$src3, s32_0ImmPred:$src2)>; // Map from p0 = pnot(p0); r0 = mux(p0, r1, #i) // => r0 = C2_muxri (p0, #i, r1) -def: Pat<(select (not (i1 PredRegs:$src1)), IntRegs:$src2, s32_0ImmPred:$src3), +def: Pat<(select (not I1:$src1), IntRegs:$src2, s32_0ImmPred:$src3), (C2_muxri PredRegs:$src1, s32_0ImmPred:$src3, IntRegs:$src2)>; // Map from p0 = pnot(p0); if (p0) jump => if (!p0) jump. -def: Pat<(brcond (not (i1 PredRegs:$src1)), bb:$offset), +def: Pat<(brcond (not I1:$src1), bb:$offset), (J2_jumpf PredRegs:$src1, bb:$offset)>; // Map from Rdd = sign_extend_inreg(Rss, i32) -> Rdd = A2_sxtw(Rss.lo). -def: Pat<(i64 (sext_inreg (i64 DoubleRegs:$src1), i32)), +def: Pat<(i64 (sext_inreg I64:$src1, i32)), (A2_sxtw (LoReg DoubleRegs:$src1))>; // Map from Rdd = sign_extend_inreg(Rss, i16) -> Rdd = A2_sxtw(A2_sxth(Rss.lo)). -def: Pat<(i64 (sext_inreg (i64 DoubleRegs:$src1), i16)), +def: Pat<(i64 (sext_inreg I64:$src1, i16)), (A2_sxtw (A2_sxth (LoReg DoubleRegs:$src1)))>; // Map from Rdd = sign_extend_inreg(Rss, i8) -> Rdd = A2_sxtw(A2_sxtb(Rss.lo)). -def: Pat<(i64 (sext_inreg (i64 DoubleRegs:$src1), i8)), +def: Pat<(i64 (sext_inreg I64:$src1, i8)), (A2_sxtw (A2_sxtb (LoReg DoubleRegs:$src1)))>; // We want to prevent emitting pnot's as much as possible. // Map brcond with an unsupported setcc to a J2_jumpf. -def : Pat <(brcond (i1 (setne (i32 IntRegs:$src1), (i32 IntRegs:$src2))), +def : Pat <(brcond (i1 (setne I32:$src1, I32:$src2)), bb:$offset), - (J2_jumpf (C2_cmpeq (i32 IntRegs:$src1), (i32 IntRegs:$src2)), + (J2_jumpf (C2_cmpeq I32:$src1, I32:$src2), bb:$offset)>; -def : Pat <(brcond (i1 (setne (i32 IntRegs:$src1), s10_0ImmPred:$src2)), +def : Pat <(brcond (i1 (setne I32:$src1, s10_0ImmPred:$src2)), bb:$offset), - (J2_jumpf (C2_cmpeqi (i32 IntRegs:$src1), s10_0ImmPred:$src2), bb:$offset)>; + (J2_jumpf (C2_cmpeqi I32:$src1, s10_0ImmPred:$src2), bb:$offset)>; -def: Pat<(brcond (i1 (setne (i1 PredRegs:$src1), (i1 -1))), bb:$offset), +def: Pat<(brcond (i1 (setne I1:$src1, (i1 -1))), bb:$offset), (J2_jumpf PredRegs:$src1, bb:$offset)>; -def: Pat<(brcond (i1 (setne (i1 PredRegs:$src1), (i1 0))), bb:$offset), +def: Pat<(brcond (i1 (setne I1:$src1, (i1 0))), bb:$offset), (J2_jumpt PredRegs:$src1, bb:$offset)>; // cmp.lt(Rs, Imm) -> !cmp.ge(Rs, Imm) -> !cmp.gt(Rs, Imm-1) -def: Pat<(brcond (i1 (setlt (i32 IntRegs:$src1), s8_0ImmPred:$src2)), bb:$offset), +def: Pat<(brcond (i1 (setlt I32:$src1, s8_0ImmPred:$src2)), bb:$offset), (J2_jumpf (C2_cmpgti IntRegs:$src1, (DEC_CONST_SIGNED s8_0ImmPred:$src2)), bb:$offset)>; // Map from a 64-bit select to an emulated 64-bit mux. // Hexagon does not support 64-bit MUXes; so emulate with combines. -def: Pat<(select (i1 PredRegs:$src1), (i64 DoubleRegs:$src2), - (i64 DoubleRegs:$src3)), +def: Pat<(select I1:$src1, I64:$src2, + I64:$src3), (A2_combinew (C2_mux PredRegs:$src1, (HiReg DoubleRegs:$src2), (HiReg DoubleRegs:$src3)), (C2_mux PredRegs:$src1, (LoReg DoubleRegs:$src2), @@ -747,112 +747,112 @@ def: Pat<(select (i1 PredRegs:$src1), (i64 DoubleRegs:$src2), // Map from a 1-bit select to logical ops. // From LegalizeDAG.cpp: (B1 ? B2 : B3) <=> (B1 & B2)|(!B1&B3). -def: Pat<(select (i1 PredRegs:$src1), (i1 PredRegs:$src2), (i1 PredRegs:$src3)), +def: Pat<(select I1:$src1, I1:$src2, I1:$src3), (C2_or (C2_and PredRegs:$src1, PredRegs:$src2), (C2_and (C2_not PredRegs:$src1), PredRegs:$src3))>; // Map for truncating from 64 immediates to 32 bit immediates. -def: Pat<(i32 (trunc (i64 DoubleRegs:$src))), +def: Pat<(i32 (trunc I64:$src)), (LoReg DoubleRegs:$src)>; // Map for truncating from i64 immediates to i1 bit immediates. -def: Pat<(i1 (trunc (i64 DoubleRegs:$src))), +def: Pat<(i1 (trunc I64:$src)), (C2_tfrrp (LoReg DoubleRegs:$src))>; // rs <= rt -> !(rs > rt). let AddedComplexity = 30 in -def: Pat<(i1 (setle (i32 IntRegs:$src1), s32_0ImmPred:$src2)), +def: Pat<(i1 (setle I32:$src1, s32_0ImmPred:$src2)), (C2_not (C2_cmpgti IntRegs:$src1, s32_0ImmPred:$src2))>; // rs <= rt -> !(rs > rt). -def : Pat<(i1 (setle (i32 IntRegs:$src1), (i32 IntRegs:$src2))), - (i1 (C2_not (C2_cmpgt (i32 IntRegs:$src1), (i32 IntRegs:$src2))))>; +def : Pat<(i1 (setle I32:$src1, I32:$src2)), + (i1 (C2_not (C2_cmpgt I32:$src1, I32:$src2)))>; // Rss <= Rtt -> !(Rss > Rtt). -def: Pat<(i1 (setle (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))), +def: Pat<(i1 (setle I64:$src1, I64:$src2)), (C2_not (C2_cmpgtp DoubleRegs:$src1, DoubleRegs:$src2))>; // Map cmpne -> cmpeq. // Hexagon_TODO: We should improve on this. // rs != rt -> !(rs == rt). let AddedComplexity = 30 in -def: Pat<(i1 (setne (i32 IntRegs:$src1), s32_0ImmPred:$src2)), +def: Pat<(i1 (setne I32:$src1, s32_0ImmPred:$src2)), (C2_not (C2_cmpeqi IntRegs:$src1, s32_0ImmPred:$src2))>; // Convert setne back to xor for hexagon since we compute w/ pred registers. -def: Pat<(i1 (setne (i1 PredRegs:$src1), (i1 PredRegs:$src2))), +def: Pat<(i1 (setne I1:$src1, I1:$src2)), (C2_xor PredRegs:$src1, PredRegs:$src2)>; // Map cmpne(Rss) -> !cmpew(Rss). // rs != rt -> !(rs == rt). -def: Pat<(i1 (setne (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))), +def: Pat<(i1 (setne I64:$src1, I64:$src2)), (C2_not (C2_cmpeqp DoubleRegs:$src1, DoubleRegs:$src2))>; // Map cmpge(Rs, Rt) -> !cmpgt(Rs, Rt). // rs >= rt -> !(rt > rs). -def : Pat <(i1 (setge (i32 IntRegs:$src1), (i32 IntRegs:$src2))), - (i1 (C2_not (i1 (C2_cmpgt (i32 IntRegs:$src2), (i32 IntRegs:$src1)))))>; +def : Pat <(i1 (setge I32:$src1, I32:$src2)), + (i1 (C2_not (i1 (C2_cmpgt I32:$src2, I32:$src1))))>; // cmpge(Rs, Imm) -> cmpgt(Rs, Imm-1) let AddedComplexity = 30 in -def: Pat<(i1 (setge (i32 IntRegs:$src1), s32_0ImmPred:$src2)), +def: Pat<(i1 (setge I32:$src1, s32_0ImmPred:$src2)), (C2_cmpgti IntRegs:$src1, (DEC_CONST_SIGNED s32_0ImmPred:$src2))>; // Map cmpge(Rss, Rtt) -> !cmpgt(Rtt, Rss). // rss >= rtt -> !(rtt > rss). -def: Pat<(i1 (setge (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))), +def: Pat<(i1 (setge I64:$src1, I64:$src2)), (C2_not (C2_cmpgtp DoubleRegs:$src2, DoubleRegs:$src1))>; // Map cmplt(Rs, Imm) -> !cmpge(Rs, Imm). // !cmpge(Rs, Imm) -> !cmpgt(Rs, Imm-1). // rs < rt -> !(rs >= rt). let AddedComplexity = 30 in -def: Pat<(i1 (setlt (i32 IntRegs:$src1), s32_0ImmPred:$src2)), +def: Pat<(i1 (setlt I32:$src1, s32_0ImmPred:$src2)), (C2_not (C2_cmpgti IntRegs:$src1, (DEC_CONST_SIGNED s32_0ImmPred:$src2)))>; // Generate cmpgeu(Rs, #0) -> cmpeq(Rs, Rs) -def: Pat<(i1 (setuge (i32 IntRegs:$src1), 0)), +def: Pat<(i1 (setuge I32:$src1, 0)), (C2_cmpeq IntRegs:$src1, IntRegs:$src1)>; // Generate cmpgeu(Rs, #u8) -> cmpgtu(Rs, #u8 -1) -def: Pat<(i1 (setuge (i32 IntRegs:$src1), u32_0ImmPred:$src2)), +def: Pat<(i1 (setuge I32:$src1, u32_0ImmPred:$src2)), (C2_cmpgtui IntRegs:$src1, (DEC_CONST_UNSIGNED u32_0ImmPred:$src2))>; // Generate cmpgtu(Rs, #u9) -def: Pat<(i1 (setugt (i32 IntRegs:$src1), u32_0ImmPred:$src2)), +def: Pat<(i1 (setugt I32:$src1, u32_0ImmPred:$src2)), (C2_cmpgtui IntRegs:$src1, u32_0ImmPred:$src2)>; // Map from Rs >= Rt -> !(Rt > Rs). // rs >= rt -> !(rt > rs). -def: Pat<(i1 (setuge (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))), +def: Pat<(i1 (setuge I64:$src1, I64:$src2)), (C2_not (C2_cmpgtup DoubleRegs:$src2, DoubleRegs:$src1))>; // Map from cmpleu(Rss, Rtt) -> !cmpgtu(Rss, Rtt-1). // Map from (Rs <= Rt) -> !(Rs > Rt). -def: Pat<(i1 (setule (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))), +def: Pat<(i1 (setule I64:$src1, I64:$src2)), (C2_not (C2_cmpgtup DoubleRegs:$src1, DoubleRegs:$src2))>; // Sign extends. // i1 -> i32 -def: Pat<(i32 (sext (i1 PredRegs:$src1))), +def: Pat<(i32 (sext I1:$src1)), (C2_muxii PredRegs:$src1, -1, 0)>; // i1 -> i64 -def: Pat<(i64 (sext (i1 PredRegs:$src1))), +def: Pat<(i64 (sext I1:$src1)), (A2_combinew (A2_tfrsi -1), (C2_muxii PredRegs:$src1, -1, 0))>; // Zero extends. // i1 -> i32 -def: Pat<(i32 (zext (i1 PredRegs:$src1))), +def: Pat<(i32 (zext I1:$src1)), (C2_muxii PredRegs:$src1, 1, 0)>; // Map from Rs = Pd to Pd = mux(Pd, #1, #0) -def: Pat<(i32 (anyext (i1 PredRegs:$src1))), +def: Pat<(i32 (anyext I1:$src1)), (C2_muxii PredRegs:$src1, 1, 0)>; // Map from Rss = Pd to Rdd = sxtw (mux(Pd, #1, #0)) -def: Pat<(i64 (anyext (i1 PredRegs:$src1))), +def: Pat<(i64 (anyext I1:$src1)), (A2_sxtw (C2_muxii PredRegs:$src1, 1, 0))>; // Clear the sign bit in a 64-bit register. @@ -903,7 +903,7 @@ def HexagonALLOCA : SDNode<"HexagonISD::ALLOCA", SDTHexagonALLOCA, [SDNPHasChain]>; -def: Pat<(HexagonALLOCA (i32 IntRegs:$Rs), (i32 imm:$A)), +def: Pat<(HexagonALLOCA I32:$Rs, (i32 imm:$A)), (PS_alloca IntRegs:$Rs, imm:$A)>; def HexagonJT: SDNode<"HexagonISD::JT", SDTIntUnaryOp>; @@ -913,106 +913,106 @@ def: Pat<(HexagonJT tjumptable:$dst), (A2_tfrsi imm:$dst)>; def: Pat<(HexagonCP tconstpool:$dst), (A2_tfrsi imm:$dst)>; let AddedComplexity = 100 in -def: Pat<(add (i32 IntRegs:$src1), (sra (i32 IntRegs:$Rs), u5_0ImmPred:$u5)), (S2_asr_i_r_acc IntRegs:$src1, IntRegs:$Rs, u5_0ImmPred:$u5)>; -def: Pat<(sub (i32 IntRegs:$src1), (sra (i32 IntRegs:$Rs), u5_0ImmPred:$u5)), (S2_asr_i_r_nac IntRegs:$src1, IntRegs:$Rs, u5_0ImmPred:$u5)>; -def: Pat<(and (i32 IntRegs:$src1), (sra (i32 IntRegs:$Rs), u5_0ImmPred:$u5)), (S2_asr_i_r_and IntRegs:$src1, IntRegs:$Rs, u5_0ImmPred:$u5)>; -def: Pat<(or (i32 IntRegs:$src1), (sra (i32 IntRegs:$Rs), u5_0ImmPred:$u5)), (S2_asr_i_r_or IntRegs:$src1, IntRegs:$Rs, u5_0ImmPred:$u5)>; +def: Pat<(add I32:$src1, (sra I32:$Rs, u5_0ImmPred:$u5)), (S2_asr_i_r_acc IntRegs:$src1, IntRegs:$Rs, u5_0ImmPred:$u5)>; +def: Pat<(sub I32:$src1, (sra I32:$Rs, u5_0ImmPred:$u5)), (S2_asr_i_r_nac IntRegs:$src1, IntRegs:$Rs, u5_0ImmPred:$u5)>; +def: Pat<(and I32:$src1, (sra I32:$Rs, u5_0ImmPred:$u5)), (S2_asr_i_r_and IntRegs:$src1, IntRegs:$Rs, u5_0ImmPred:$u5)>; +def: Pat<(or I32:$src1, (sra I32:$Rs, u5_0ImmPred:$u5)), (S2_asr_i_r_or IntRegs:$src1, IntRegs:$Rs, u5_0ImmPred:$u5)>; let AddedComplexity = 100 in -def: Pat<(add (i64 DoubleRegs:$src1), (sra (i64 DoubleRegs:$Rs), u6_0ImmPred:$u5)), (S2_asr_i_p_acc DoubleRegs:$src1, DoubleRegs:$Rs, u6_0ImmPred:$u5)>; -def: Pat<(sub (i64 DoubleRegs:$src1), (sra (i64 DoubleRegs:$Rs), u6_0ImmPred:$u5)), (S2_asr_i_p_nac DoubleRegs:$src1, DoubleRegs:$Rs, u6_0ImmPred:$u5)>; -def: Pat<(and (i64 DoubleRegs:$src1), (sra (i64 DoubleRegs:$Rs), u6_0ImmPred:$u5)), (S2_asr_i_p_and DoubleRegs:$src1, DoubleRegs:$Rs, u6_0ImmPred:$u5)>; -def: Pat<(or (i64 DoubleRegs:$src1), (sra (i64 DoubleRegs:$Rs), u6_0ImmPred:$u5)), (S2_asr_i_p_or DoubleRegs:$src1, DoubleRegs:$Rs, u6_0ImmPred:$u5)>; +def: Pat<(add I64:$src1, (sra I64:$Rs, u6_0ImmPred:$u5)), (S2_asr_i_p_acc DoubleRegs:$src1, DoubleRegs:$Rs, u6_0ImmPred:$u5)>; +def: Pat<(sub I64:$src1, (sra I64:$Rs, u6_0ImmPred:$u5)), (S2_asr_i_p_nac DoubleRegs:$src1, DoubleRegs:$Rs, u6_0ImmPred:$u5)>; +def: Pat<(and I64:$src1, (sra I64:$Rs, u6_0ImmPred:$u5)), (S2_asr_i_p_and DoubleRegs:$src1, DoubleRegs:$Rs, u6_0ImmPred:$u5)>; +def: Pat<(or I64:$src1, (sra I64:$Rs, u6_0ImmPred:$u5)), (S2_asr_i_p_or DoubleRegs:$src1, DoubleRegs:$Rs, u6_0ImmPred:$u5)>; let AddedComplexity = 100 in -def: Pat<(add (i32 IntRegs:$src1), (srl (i32 IntRegs:$Rs), u5_0ImmPred:$u5)), (S2_lsr_i_r_acc IntRegs:$src1, IntRegs:$Rs, u5_0ImmPred:$u5)>; -def: Pat<(sub (i32 IntRegs:$src1), (srl (i32 IntRegs:$Rs), u5_0ImmPred:$u5)), (S2_lsr_i_r_nac IntRegs:$src1, IntRegs:$Rs, u5_0ImmPred:$u5)>; -def: Pat<(and (i32 IntRegs:$src1), (srl (i32 IntRegs:$Rs), u5_0ImmPred:$u5)), (S2_lsr_i_r_and IntRegs:$src1, IntRegs:$Rs, u5_0ImmPred:$u5)>; -def: Pat<(or (i32 IntRegs:$src1), (srl (i32 IntRegs:$Rs), u5_0ImmPred:$u5)), (S2_lsr_i_r_or IntRegs:$src1, IntRegs:$Rs, u5_0ImmPred:$u5)>; +def: Pat<(add I32:$src1, (srl I32:$Rs, u5_0ImmPred:$u5)), (S2_lsr_i_r_acc IntRegs:$src1, IntRegs:$Rs, u5_0ImmPred:$u5)>; +def: Pat<(sub I32:$src1, (srl I32:$Rs, u5_0ImmPred:$u5)), (S2_lsr_i_r_nac IntRegs:$src1, IntRegs:$Rs, u5_0ImmPred:$u5)>; +def: Pat<(and I32:$src1, (srl I32:$Rs, u5_0ImmPred:$u5)), (S2_lsr_i_r_and IntRegs:$src1, IntRegs:$Rs, u5_0ImmPred:$u5)>; +def: Pat<(or I32:$src1, (srl I32:$Rs, u5_0ImmPred:$u5)), (S2_lsr_i_r_or IntRegs:$src1, IntRegs:$Rs, u5_0ImmPred:$u5)>; let AddedComplexity = 100 in -def: Pat<(xor (i32 IntRegs:$src1), (srl (i32 IntRegs:$Rs), u5_0ImmPred:$u5)), (S2_lsr_i_r_xacc IntRegs:$src1, IntRegs:$Rs, u5_0ImmPred:$u5)>; +def: Pat<(xor I32:$src1, (srl I32:$Rs, u5_0ImmPred:$u5)), (S2_lsr_i_r_xacc IntRegs:$src1, IntRegs:$Rs, u5_0ImmPred:$u5)>; let AddedComplexity = 100 in -def: Pat<(add (i64 DoubleRegs:$src1), (srl (i64 DoubleRegs:$Rs), u6_0ImmPred:$u5)), (S2_lsr_i_p_acc DoubleRegs:$src1, DoubleRegs:$Rs, u6_0ImmPred:$u5)>; -def: Pat<(sub (i64 DoubleRegs:$src1), (srl (i64 DoubleRegs:$Rs), u6_0ImmPred:$u5)), (S2_lsr_i_p_nac DoubleRegs:$src1, DoubleRegs:$Rs, u6_0ImmPred:$u5)>; -def: Pat<(and (i64 DoubleRegs:$src1), (srl (i64 DoubleRegs:$Rs), u6_0ImmPred:$u5)), (S2_lsr_i_p_and DoubleRegs:$src1, DoubleRegs:$Rs, u6_0ImmPred:$u5)>; -def: Pat<(or (i64 DoubleRegs:$src1), (srl (i64 DoubleRegs:$Rs), u6_0ImmPred:$u5)), (S2_lsr_i_p_or DoubleRegs:$src1, DoubleRegs:$Rs, u6_0ImmPred:$u5)>; +def: Pat<(add I64:$src1, (srl I64:$Rs, u6_0ImmPred:$u5)), (S2_lsr_i_p_acc DoubleRegs:$src1, DoubleRegs:$Rs, u6_0ImmPred:$u5)>; +def: Pat<(sub I64:$src1, (srl I64:$Rs, u6_0ImmPred:$u5)), (S2_lsr_i_p_nac DoubleRegs:$src1, DoubleRegs:$Rs, u6_0ImmPred:$u5)>; +def: Pat<(and I64:$src1, (srl I64:$Rs, u6_0ImmPred:$u5)), (S2_lsr_i_p_and DoubleRegs:$src1, DoubleRegs:$Rs, u6_0ImmPred:$u5)>; +def: Pat<(or I64:$src1, (srl I64:$Rs, u6_0ImmPred:$u5)), (S2_lsr_i_p_or DoubleRegs:$src1, DoubleRegs:$Rs, u6_0ImmPred:$u5)>; let AddedComplexity = 100 in -def: Pat<(xor (i64 DoubleRegs:$src1), (srl (i64 DoubleRegs:$Rs), u6_0ImmPred:$u5)), (S2_lsr_i_p_xacc DoubleRegs:$src1, DoubleRegs:$Rs, u6_0ImmPred:$u5)>; +def: Pat<(xor I64:$src1, (srl I64:$Rs, u6_0ImmPred:$u5)), (S2_lsr_i_p_xacc DoubleRegs:$src1, DoubleRegs:$Rs, u6_0ImmPred:$u5)>; let AddedComplexity = 100 in -def: Pat<(add (i32 IntRegs:$src1), (shl (i32 IntRegs:$Rs), u5_0ImmPred:$u5)), (S2_asl_i_r_acc IntRegs:$src1, IntRegs:$Rs, u5_0ImmPred:$u5)>; -def: Pat<(sub (i32 IntRegs:$src1), (shl (i32 IntRegs:$Rs), u5_0ImmPred:$u5)), (S2_asl_i_r_nac IntRegs:$src1, IntRegs:$Rs, u5_0ImmPred:$u5)>; -def: Pat<(and (i32 IntRegs:$src1), (shl (i32 IntRegs:$Rs), u5_0ImmPred:$u5)), (S2_asl_i_r_and IntRegs:$src1, IntRegs:$Rs, u5_0ImmPred:$u5)>; -def: Pat<(or (i32 IntRegs:$src1), (shl (i32 IntRegs:$Rs), u5_0ImmPred:$u5)), (S2_asl_i_r_or IntRegs:$src1, IntRegs:$Rs, u5_0ImmPred:$u5)>; +def: Pat<(add I32:$src1, (shl I32:$Rs, u5_0ImmPred:$u5)), (S2_asl_i_r_acc IntRegs:$src1, IntRegs:$Rs, u5_0ImmPred:$u5)>; +def: Pat<(sub I32:$src1, (shl I32:$Rs, u5_0ImmPred:$u5)), (S2_asl_i_r_nac IntRegs:$src1, IntRegs:$Rs, u5_0ImmPred:$u5)>; +def: Pat<(and I32:$src1, (shl I32:$Rs, u5_0ImmPred:$u5)), (S2_asl_i_r_and IntRegs:$src1, IntRegs:$Rs, u5_0ImmPred:$u5)>; +def: Pat<(or I32:$src1, (shl I32:$Rs, u5_0ImmPred:$u5)), (S2_asl_i_r_or IntRegs:$src1, IntRegs:$Rs, u5_0ImmPred:$u5)>; let AddedComplexity = 100 in -def: Pat<(xor (i32 IntRegs:$src1), (shl (i32 IntRegs:$Rs), u5_0ImmPred:$u5)), (S2_asl_i_r_xacc IntRegs:$src1, IntRegs:$Rs, u5_0ImmPred:$u5)>; +def: Pat<(xor I32:$src1, (shl I32:$Rs, u5_0ImmPred:$u5)), (S2_asl_i_r_xacc IntRegs:$src1, IntRegs:$Rs, u5_0ImmPred:$u5)>; let AddedComplexity = 100 in -def: Pat<(add (i64 DoubleRegs:$src1), (shl (i64 DoubleRegs:$Rs), u6_0ImmPred:$u5)), (S2_asl_i_p_acc DoubleRegs:$src1, DoubleRegs:$Rs, u6_0ImmPred:$u5)>; -def: Pat<(sub (i64 DoubleRegs:$src1), (shl (i64 DoubleRegs:$Rs), u6_0ImmPred:$u5)), (S2_asl_i_p_nac DoubleRegs:$src1, DoubleRegs:$Rs, u6_0ImmPred:$u5)>; -def: Pat<(and (i64 DoubleRegs:$src1), (shl (i64 DoubleRegs:$Rs), u6_0ImmPred:$u5)), (S2_asl_i_p_and DoubleRegs:$src1, DoubleRegs:$Rs, u6_0ImmPred:$u5)>; -def: Pat<(or (i64 DoubleRegs:$src1), (shl (i64 DoubleRegs:$Rs), u6_0ImmPred:$u5)), (S2_asl_i_p_or DoubleRegs:$src1, DoubleRegs:$Rs, u6_0ImmPred:$u5)>; +def: Pat<(add I64:$src1, (shl I64:$Rs, u6_0ImmPred:$u5)), (S2_asl_i_p_acc DoubleRegs:$src1, DoubleRegs:$Rs, u6_0ImmPred:$u5)>; +def: Pat<(sub I64:$src1, (shl I64:$Rs, u6_0ImmPred:$u5)), (S2_asl_i_p_nac DoubleRegs:$src1, DoubleRegs:$Rs, u6_0ImmPred:$u5)>; +def: Pat<(and I64:$src1, (shl I64:$Rs, u6_0ImmPred:$u5)), (S2_asl_i_p_and DoubleRegs:$src1, DoubleRegs:$Rs, u6_0ImmPred:$u5)>; +def: Pat<(or I64:$src1, (shl I64:$Rs, u6_0ImmPred:$u5)), (S2_asl_i_p_or DoubleRegs:$src1, DoubleRegs:$Rs, u6_0ImmPred:$u5)>; let AddedComplexity = 100 in -def: Pat<(xor (i64 DoubleRegs:$src1), (shl (i64 DoubleRegs:$Rs), u6_0ImmPred:$u5)), (S2_asl_i_p_xacc DoubleRegs:$src1, DoubleRegs:$Rs, u6_0ImmPred:$u5)>; +def: Pat<(xor I64:$src1, (shl I64:$Rs, u6_0ImmPred:$u5)), (S2_asl_i_p_xacc DoubleRegs:$src1, DoubleRegs:$Rs, u6_0ImmPred:$u5)>; let AddedComplexity = 100 in -def: Pat<(add (i32 IntRegs:$src1), (shl (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))), (S2_asl_r_r_acc IntRegs:$src1, IntRegs:$Rs, IntRegs:$Rt)>; -def: Pat<(sub (i32 IntRegs:$src1), (shl (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))), (S2_asl_r_r_nac IntRegs:$src1, IntRegs:$Rs, IntRegs:$Rt)>; -def: Pat<(and (i32 IntRegs:$src1), (shl (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))), (S2_asl_r_r_and IntRegs:$src1, IntRegs:$Rs, IntRegs:$Rt)>; -def: Pat<(or (i32 IntRegs:$src1), (shl (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))), (S2_asl_r_r_or IntRegs:$src1, IntRegs:$Rs, IntRegs:$Rt)>; +def: Pat<(add I32:$src1, (shl I32:$Rs, I32:$Rt)), (S2_asl_r_r_acc IntRegs:$src1, IntRegs:$Rs, IntRegs:$Rt)>; +def: Pat<(sub I32:$src1, (shl I32:$Rs, I32:$Rt)), (S2_asl_r_r_nac IntRegs:$src1, IntRegs:$Rs, IntRegs:$Rt)>; +def: Pat<(and I32:$src1, (shl I32:$Rs, I32:$Rt)), (S2_asl_r_r_and IntRegs:$src1, IntRegs:$Rs, IntRegs:$Rt)>; +def: Pat<(or I32:$src1, (shl I32:$Rs, I32:$Rt)), (S2_asl_r_r_or IntRegs:$src1, IntRegs:$Rs, IntRegs:$Rt)>; let AddedComplexity = 100 in -def: Pat<(add (i64 DoubleRegs:$src1), (shl (i64 DoubleRegs:$Rs), (i32 IntRegs:$Rt))), (S2_asl_r_p_acc DoubleRegs:$src1, DoubleRegs:$Rs, IntRegs:$Rt)>; -def: Pat<(sub (i64 DoubleRegs:$src1), (shl (i64 DoubleRegs:$Rs), (i32 IntRegs:$Rt))), (S2_asl_r_p_nac DoubleRegs:$src1, DoubleRegs:$Rs, IntRegs:$Rt)>; -def: Pat<(and (i64 DoubleRegs:$src1), (shl (i64 DoubleRegs:$Rs), (i32 IntRegs:$Rt))), (S2_asl_r_p_and DoubleRegs:$src1, DoubleRegs:$Rs, IntRegs:$Rt)>; -def: Pat<(or (i64 DoubleRegs:$src1), (shl (i64 DoubleRegs:$Rs), (i32 IntRegs:$Rt))), (S2_asl_r_p_or DoubleRegs:$src1, DoubleRegs:$Rs, IntRegs:$Rt)>; -def: Pat<(xor (i64 DoubleRegs:$src1), (shl (i64 DoubleRegs:$Rs), (i32 IntRegs:$Rt))), (S2_asl_r_p_xor DoubleRegs:$src1, DoubleRegs:$Rs, IntRegs:$Rt)>; +def: Pat<(add I64:$src1, (shl I64:$Rs, I32:$Rt)), (S2_asl_r_p_acc DoubleRegs:$src1, DoubleRegs:$Rs, IntRegs:$Rt)>; +def: Pat<(sub I64:$src1, (shl I64:$Rs, I32:$Rt)), (S2_asl_r_p_nac DoubleRegs:$src1, DoubleRegs:$Rs, IntRegs:$Rt)>; +def: Pat<(and I64:$src1, (shl I64:$Rs, I32:$Rt)), (S2_asl_r_p_and DoubleRegs:$src1, DoubleRegs:$Rs, IntRegs:$Rt)>; +def: Pat<(or I64:$src1, (shl I64:$Rs, I32:$Rt)), (S2_asl_r_p_or DoubleRegs:$src1, DoubleRegs:$Rs, IntRegs:$Rt)>; +def: Pat<(xor I64:$src1, (shl I64:$Rs, I32:$Rt)), (S2_asl_r_p_xor DoubleRegs:$src1, DoubleRegs:$Rs, IntRegs:$Rt)>; let AddedComplexity = 100 in -def: Pat<(add (i32 IntRegs:$src1), (sra (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))), (S2_asr_r_r_acc IntRegs:$src1, IntRegs:$Rs, IntRegs:$Rt)>; -def: Pat<(sub (i32 IntRegs:$src1), (sra (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))), (S2_asr_r_r_nac IntRegs:$src1, IntRegs:$Rs, IntRegs:$Rt)>; -def: Pat<(and (i32 IntRegs:$src1), (sra (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))), (S2_asr_r_r_and IntRegs:$src1, IntRegs:$Rs, IntRegs:$Rt)>; -def: Pat<(or (i32 IntRegs:$src1), (sra (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))), (S2_asr_r_r_or IntRegs:$src1, IntRegs:$Rs, IntRegs:$Rt)>; +def: Pat<(add I32:$src1, (sra I32:$Rs, I32:$Rt)), (S2_asr_r_r_acc IntRegs:$src1, IntRegs:$Rs, IntRegs:$Rt)>; +def: Pat<(sub I32:$src1, (sra I32:$Rs, I32:$Rt)), (S2_asr_r_r_nac IntRegs:$src1, IntRegs:$Rs, IntRegs:$Rt)>; +def: Pat<(and I32:$src1, (sra I32:$Rs, I32:$Rt)), (S2_asr_r_r_and IntRegs:$src1, IntRegs:$Rs, IntRegs:$Rt)>; +def: Pat<(or I32:$src1, (sra I32:$Rs, I32:$Rt)), (S2_asr_r_r_or IntRegs:$src1, IntRegs:$Rs, IntRegs:$Rt)>; let AddedComplexity = 100 in -def: Pat<(add (i64 DoubleRegs:$src1), (sra (i64 DoubleRegs:$Rs), (i32 IntRegs:$Rt))), (S2_asr_r_p_acc DoubleRegs:$src1, DoubleRegs:$Rs, IntRegs:$Rt)>; -def: Pat<(sub (i64 DoubleRegs:$src1), (sra (i64 DoubleRegs:$Rs), (i32 IntRegs:$Rt))), (S2_asr_r_p_nac DoubleRegs:$src1, DoubleRegs:$Rs, IntRegs:$Rt)>; -def: Pat<(and (i64 DoubleRegs:$src1), (sra (i64 DoubleRegs:$Rs), (i32 IntRegs:$Rt))), (S2_asr_r_p_and DoubleRegs:$src1, DoubleRegs:$Rs, IntRegs:$Rt)>; -def: Pat<(or (i64 DoubleRegs:$src1), (sra (i64 DoubleRegs:$Rs), (i32 IntRegs:$Rt))), (S2_asr_r_p_or DoubleRegs:$src1, DoubleRegs:$Rs, IntRegs:$Rt)>; -def: Pat<(xor (i64 DoubleRegs:$src1), (sra (i64 DoubleRegs:$Rs), (i32 IntRegs:$Rt))), (S2_asr_r_p_xor DoubleRegs:$src1, DoubleRegs:$Rs, IntRegs:$Rt)>; +def: Pat<(add I64:$src1, (sra I64:$Rs, I32:$Rt)), (S2_asr_r_p_acc DoubleRegs:$src1, DoubleRegs:$Rs, IntRegs:$Rt)>; +def: Pat<(sub I64:$src1, (sra I64:$Rs, I32:$Rt)), (S2_asr_r_p_nac DoubleRegs:$src1, DoubleRegs:$Rs, IntRegs:$Rt)>; +def: Pat<(and I64:$src1, (sra I64:$Rs, I32:$Rt)), (S2_asr_r_p_and DoubleRegs:$src1, DoubleRegs:$Rs, IntRegs:$Rt)>; +def: Pat<(or I64:$src1, (sra I64:$Rs, I32:$Rt)), (S2_asr_r_p_or DoubleRegs:$src1, DoubleRegs:$Rs, IntRegs:$Rt)>; +def: Pat<(xor I64:$src1, (sra I64:$Rs, I32:$Rt)), (S2_asr_r_p_xor DoubleRegs:$src1, DoubleRegs:$Rs, IntRegs:$Rt)>; let AddedComplexity = 100 in -def: Pat<(add (i32 IntRegs:$src1), (srl (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))), (S2_lsr_r_r_acc IntRegs:$src1, IntRegs:$Rs, IntRegs:$Rt)>; -def: Pat<(sub (i32 IntRegs:$src1), (srl (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))), (S2_lsr_r_r_nac IntRegs:$src1, IntRegs:$Rs, IntRegs:$Rt)>; -def: Pat<(and (i32 IntRegs:$src1), (srl (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))), (S2_lsr_r_r_and IntRegs:$src1, IntRegs:$Rs, IntRegs:$Rt)>; -def: Pat<(or (i32 IntRegs:$src1), (srl (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))), (S2_lsr_r_r_or IntRegs:$src1, IntRegs:$Rs, IntRegs:$Rt)>; +def: Pat<(add I32:$src1, (srl I32:$Rs, I32:$Rt)), (S2_lsr_r_r_acc IntRegs:$src1, IntRegs:$Rs, IntRegs:$Rt)>; +def: Pat<(sub I32:$src1, (srl I32:$Rs, I32:$Rt)), (S2_lsr_r_r_nac IntRegs:$src1, IntRegs:$Rs, IntRegs:$Rt)>; +def: Pat<(and I32:$src1, (srl I32:$Rs, I32:$Rt)), (S2_lsr_r_r_and IntRegs:$src1, IntRegs:$Rs, IntRegs:$Rt)>; +def: Pat<(or I32:$src1, (srl I32:$Rs, I32:$Rt)), (S2_lsr_r_r_or IntRegs:$src1, IntRegs:$Rs, IntRegs:$Rt)>; let AddedComplexity = 100 in -def: Pat<(add (i64 DoubleRegs:$src1), (srl (i64 DoubleRegs:$Rs), (i32 IntRegs:$Rt))), (S2_lsr_r_p_acc DoubleRegs:$src1, DoubleRegs:$Rs, IntRegs:$Rt)>; -def: Pat<(sub (i64 DoubleRegs:$src1), (srl (i64 DoubleRegs:$Rs), (i32 IntRegs:$Rt))), (S2_lsr_r_p_nac DoubleRegs:$src1, DoubleRegs:$Rs, IntRegs:$Rt)>; -def: Pat<(and (i64 DoubleRegs:$src1), (srl (i64 DoubleRegs:$Rs), (i32 IntRegs:$Rt))), (S2_lsr_r_p_and DoubleRegs:$src1, DoubleRegs:$Rs, IntRegs:$Rt)>; -def: Pat<(or (i64 DoubleRegs:$src1), (srl (i64 DoubleRegs:$Rs), (i32 IntRegs:$Rt))), (S2_lsr_r_p_or DoubleRegs:$src1, DoubleRegs:$Rs, IntRegs:$Rt)>; -def: Pat<(xor (i64 DoubleRegs:$src1), (srl (i64 DoubleRegs:$Rs), (i32 IntRegs:$Rt))), (S2_lsr_r_p_xor DoubleRegs:$src1, DoubleRegs:$Rs, IntRegs:$Rt)>; +def: Pat<(add I64:$src1, (srl I64:$Rs, I32:$Rt)), (S2_lsr_r_p_acc DoubleRegs:$src1, DoubleRegs:$Rs, IntRegs:$Rt)>; +def: Pat<(sub I64:$src1, (srl I64:$Rs, I32:$Rt)), (S2_lsr_r_p_nac DoubleRegs:$src1, DoubleRegs:$Rs, IntRegs:$Rt)>; +def: Pat<(and I64:$src1, (srl I64:$Rs, I32:$Rt)), (S2_lsr_r_p_and DoubleRegs:$src1, DoubleRegs:$Rs, IntRegs:$Rt)>; +def: Pat<(or I64:$src1, (srl I64:$Rs, I32:$Rt)), (S2_lsr_r_p_or DoubleRegs:$src1, DoubleRegs:$Rs, IntRegs:$Rt)>; +def: Pat<(xor I64:$src1, (srl I64:$Rs, I32:$Rt)), (S2_lsr_r_p_xor DoubleRegs:$src1, DoubleRegs:$Rs, IntRegs:$Rt)>; let AddedComplexity = 100 in -def: Pat<(add (i32 IntRegs:$src1), (shl (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))), (S2_lsl_r_r_acc IntRegs:$src1, IntRegs:$Rs, IntRegs:$Rt)>; -def: Pat<(sub (i32 IntRegs:$src1), (shl (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))), (S2_lsl_r_r_nac IntRegs:$src1, IntRegs:$Rs, IntRegs:$Rt)>; -def: Pat<(and (i32 IntRegs:$src1), (shl (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))), (S2_lsl_r_r_and IntRegs:$src1, IntRegs:$Rs, IntRegs:$Rt)>; -def: Pat<(or (i32 IntRegs:$src1), (shl (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))), (S2_lsl_r_r_or IntRegs:$src1, IntRegs:$Rs, IntRegs:$Rt)>; +def: Pat<(add I32:$src1, (shl I32:$Rs, I32:$Rt)), (S2_lsl_r_r_acc IntRegs:$src1, IntRegs:$Rs, IntRegs:$Rt)>; +def: Pat<(sub I32:$src1, (shl I32:$Rs, I32:$Rt)), (S2_lsl_r_r_nac IntRegs:$src1, IntRegs:$Rs, IntRegs:$Rt)>; +def: Pat<(and I32:$src1, (shl I32:$Rs, I32:$Rt)), (S2_lsl_r_r_and IntRegs:$src1, IntRegs:$Rs, IntRegs:$Rt)>; +def: Pat<(or I32:$src1, (shl I32:$Rs, I32:$Rt)), (S2_lsl_r_r_or IntRegs:$src1, IntRegs:$Rs, IntRegs:$Rt)>; let AddedComplexity = 100 in -def: Pat<(add (i64 DoubleRegs:$src1), (shl (i64 DoubleRegs:$Rs), (i32 IntRegs:$Rt))), (S2_lsl_r_p_acc DoubleRegs:$src1, DoubleRegs:$Rs, IntRegs:$Rt)>; -def: Pat<(sub (i64 DoubleRegs:$src1), (shl (i64 DoubleRegs:$Rs), (i32 IntRegs:$Rt))), (S2_lsl_r_p_nac DoubleRegs:$src1, DoubleRegs:$Rs, IntRegs:$Rt)>; -def: Pat<(and (i64 DoubleRegs:$src1), (shl (i64 DoubleRegs:$Rs), (i32 IntRegs:$Rt))), (S2_lsl_r_p_and DoubleRegs:$src1, DoubleRegs:$Rs, IntRegs:$Rt)>; -def: Pat<(or (i64 DoubleRegs:$src1), (shl (i64 DoubleRegs:$Rs), (i32 IntRegs:$Rt))), (S2_lsl_r_p_or DoubleRegs:$src1, DoubleRegs:$Rs, IntRegs:$Rt)>; -def: Pat<(xor (i64 DoubleRegs:$src1), (shl (i64 DoubleRegs:$Rs), (i32 IntRegs:$Rt))), (S2_lsl_r_p_xor DoubleRegs:$src1, DoubleRegs:$Rs, IntRegs:$Rt)>; - -def: Pat<(sra (i64 DoubleRegs:$src1), (i32 IntRegs:$src2)), (S2_asr_r_p DoubleRegs:$src1, IntRegs:$src2)>; -def: Pat<(srl (i64 DoubleRegs:$src1), (i32 IntRegs:$src2)), (S2_lsr_r_p DoubleRegs:$src1, IntRegs:$src2)>; -def: Pat<(shl (i64 DoubleRegs:$src1), (i32 IntRegs:$src2)), (S2_asl_r_p DoubleRegs:$src1, IntRegs:$src2)>; -def: Pat<(shl (i64 DoubleRegs:$src1), (i32 IntRegs:$src2)), (S2_lsl_r_p DoubleRegs:$src1, IntRegs:$src2)>; - -def: Pat<(sra (i32 IntRegs:$src1), (i32 IntRegs:$src2)), (S2_asr_r_r IntRegs:$src1, IntRegs:$src2)>; -def: Pat<(srl (i32 IntRegs:$src1), (i32 IntRegs:$src2)), (S2_lsr_r_r IntRegs:$src1, IntRegs:$src2)>; -def: Pat<(shl (i32 IntRegs:$src1), (i32 IntRegs:$src2)), (S2_asl_r_r IntRegs:$src1, IntRegs:$src2)>; -def: Pat<(shl (i32 IntRegs:$src1), (i32 IntRegs:$src2)), (S2_lsl_r_r IntRegs:$src1, IntRegs:$src2)>; +def: Pat<(add I64:$src1, (shl I64:$Rs, I32:$Rt)), (S2_lsl_r_p_acc DoubleRegs:$src1, DoubleRegs:$Rs, IntRegs:$Rt)>; +def: Pat<(sub I64:$src1, (shl I64:$Rs, I32:$Rt)), (S2_lsl_r_p_nac DoubleRegs:$src1, DoubleRegs:$Rs, IntRegs:$Rt)>; +def: Pat<(and I64:$src1, (shl I64:$Rs, I32:$Rt)), (S2_lsl_r_p_and DoubleRegs:$src1, DoubleRegs:$Rs, IntRegs:$Rt)>; +def: Pat<(or I64:$src1, (shl I64:$Rs, I32:$Rt)), (S2_lsl_r_p_or DoubleRegs:$src1, DoubleRegs:$Rs, IntRegs:$Rt)>; +def: Pat<(xor I64:$src1, (shl I64:$Rs, I32:$Rt)), (S2_lsl_r_p_xor DoubleRegs:$src1, DoubleRegs:$Rs, IntRegs:$Rt)>; + +def: Pat<(sra I64:$src1, I32:$src2), (S2_asr_r_p DoubleRegs:$src1, IntRegs:$src2)>; +def: Pat<(srl I64:$src1, I32:$src2), (S2_lsr_r_p DoubleRegs:$src1, IntRegs:$src2)>; +def: Pat<(shl I64:$src1, I32:$src2), (S2_asl_r_p DoubleRegs:$src1, IntRegs:$src2)>; +def: Pat<(shl I64:$src1, I32:$src2), (S2_lsl_r_p DoubleRegs:$src1, IntRegs:$src2)>; + +def: Pat<(sra I32:$src1, I32:$src2), (S2_asr_r_r IntRegs:$src1, IntRegs:$src2)>; +def: Pat<(srl I32:$src1, I32:$src2), (S2_lsr_r_r IntRegs:$src1, IntRegs:$src2)>; +def: Pat<(shl I32:$src1, I32:$src2), (S2_asl_r_r IntRegs:$src1, IntRegs:$src2)>; +def: Pat<(shl I32:$src1, I32:$src2), (S2_lsl_r_r IntRegs:$src1, IntRegs:$src2)>; def SDTHexagonINSERT: SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, @@ -1062,14 +1062,14 @@ def: Pat<(HexagonEXTRACTURP I64:$src1, I64:$src2), (S2_extractup_rp I64:$src1, I64:$src2)>; // Change the sign of the immediate for Rd=-mpyi(Rs,#u8) -def: Pat<(mul (i32 IntRegs:$src1), (ineg n8_0ImmPred:$src2)), +def: Pat<(mul I32:$src1, (ineg n8_0ImmPred:$src2)), (M2_mpysin IntRegs:$src1, u8_0ImmPred:$src2)>; multiclass MinMax_pats_p { defm: T_MinMax_pats; } -def: Pat<(add (i64 (sext (i32 IntRegs:$Rs))), (i64 DoubleRegs:$Rt)), +def: Pat<(add (i64 (sext I32:$Rs)), I64:$Rt), (A2_addsp IntRegs:$Rs, DoubleRegs:$Rt)>; let AddedComplexity = 200 in { @@ -1138,28 +1138,28 @@ def: T_cmp32_rr_pat, i1>; def: T_cmp32_rr_pat, i1>; let AddedComplexity = 100 in { - def: Pat<(i1 (seteq (and (xor (i32 IntRegs:$Rs), (i32 IntRegs:$Rt)), + def: Pat<(i1 (seteq (and (xor I32:$Rs, I32:$Rt), 255), 0)), (A4_cmpbeq IntRegs:$Rs, IntRegs:$Rt)>; - def: Pat<(i1 (setne (and (xor (i32 IntRegs:$Rs), (i32 IntRegs:$Rt)), + def: Pat<(i1 (setne (and (xor I32:$Rs, I32:$Rt), 255), 0)), (C2_not (A4_cmpbeq IntRegs:$Rs, IntRegs:$Rt))>; - def: Pat<(i1 (seteq (and (xor (i32 IntRegs:$Rs), (i32 IntRegs:$Rt)), + def: Pat<(i1 (seteq (and (xor I32:$Rs, I32:$Rt), 65535), 0)), (A4_cmpheq IntRegs:$Rs, IntRegs:$Rt)>; - def: Pat<(i1 (setne (and (xor (i32 IntRegs:$Rs), (i32 IntRegs:$Rt)), + def: Pat<(i1 (setne (and (xor I32:$Rs, I32:$Rt), 65535), 0)), (C2_not (A4_cmpheq IntRegs:$Rs, IntRegs:$Rt))>; } -def: Pat<(i32 (zext (i1 (seteq (i32 IntRegs:$Rs), s32_0ImmPred:$s8)))), +def: Pat<(i32 (zext (i1 (seteq I32:$Rs, s32_0ImmPred:$s8)))), (A4_rcmpeqi IntRegs:$Rs, s32_0ImmPred:$s8)>; -def: Pat<(i32 (zext (i1 (setne (i32 IntRegs:$Rs), s32_0ImmPred:$s8)))), +def: Pat<(i32 (zext (i1 (setne I32:$Rs, s32_0ImmPred:$s8)))), (A4_rcmpneqi IntRegs:$Rs, s32_0ImmPred:$s8)>; // Preserve the S2_tstbit_r generation -def: Pat<(i32 (zext (i1 (setne (i32 (and (i32 (shl 1, (i32 IntRegs:$src2))), - (i32 IntRegs:$src1))), 0)))), +def: Pat<(i32 (zext (i1 (setne (i32 (and (i32 (shl 1, I32:$src2)), + I32:$src1)), 0)))), (C2_muxii (S2_tstbit_r IntRegs:$src1, IntRegs:$src2), 1, 0)>; // The complexity of the combines involving immediates should be greater @@ -1182,9 +1182,9 @@ def: Pat<(HexagonCOMBINE s32_0ImmPred:$s8, s8_0ImmPred:$S8), } -def Zext64: OutPatFrag<(ops node:$Rs), +def ToZext64: OutPatFrag<(ops node:$Rs), (i64 (A4_combineir 0, (i32 $Rs)))>; -def Sext64: OutPatFrag<(ops node:$Rs), +def ToSext64: OutPatFrag<(ops node:$Rs), (i64 (A2_sxtw (i32 $Rs)))>; // Patterns to generate indexed loads with different forms of the address: @@ -1199,21 +1199,21 @@ multiclass Loadxm_pat; def: Pat<(VT (Load (add IntRegs:$Rs, ImmPred:$Off))), (VT (ValueMod (MI IntRegs:$Rs, imm:$Off)))>; - def: Pat<(VT (Load (i32 IntRegs:$Rs))), + def: Pat<(VT (Load I32:$Rs)), (VT (ValueMod (MI IntRegs:$Rs, 0)))>; } -defm: Loadxm_pat; -defm: Loadxm_pat; -defm: Loadxm_pat; -defm: Loadxm_pat; -defm: Loadxm_pat; -defm: Loadxm_pat; -defm: Loadxm_pat; -defm: Loadxm_pat; +defm: Loadxm_pat; +defm: Loadxm_pat; +defm: Loadxm_pat; +defm: Loadxm_pat; +defm: Loadxm_pat; +defm: Loadxm_pat; +defm: Loadxm_pat; +defm: Loadxm_pat; // Map Rdd = anyext(Rs) -> Rdd = combine(#0, Rs). -def: Pat<(i64 (anyext (i32 IntRegs:$src1))), (Zext64 IntRegs:$src1)>; +def: Pat<(i64 (anyext I32:$src1)), (ToZext64 IntRegs:$src1)>; multiclass T_LoadAbsReg_Pat { def : Pat <(VT (ldOp (add (shl IntRegs:$src1, u2_0ImmPred:$src2), @@ -1255,8 +1255,8 @@ defm : T_LoadAbsReg_Pat ; // immediate value. Immediate value is used to left-shift the second // register operand. class Loadxs_pat - : Pat<(VT (Load (add (i32 IntRegs:$Rs), - (i32 (shl (i32 IntRegs:$Rt), u2_0ImmPred:$u2))))), + : Pat<(VT (Load (add I32:$Rs, + (i32 (shl I32:$Rt, u2_0ImmPred:$u2))))), (VT (MI IntRegs:$Rs, IntRegs:$Rt, imm:$u2))>; let AddedComplexity = 40 in { @@ -1273,7 +1273,7 @@ let AddedComplexity = 40 in { // 'def pats' for load instruction base + register offset and // zero immediate value. class Loadxs_simple_pat - : Pat<(VT (Load (add (i32 IntRegs:$Rs), (i32 IntRegs:$Rt)))), + : Pat<(VT (Load (add I32:$Rs, I32:$Rt))), (VT (MI IntRegs:$Rs, IntRegs:$Rt, 0))>; let AddedComplexity = 20 in { @@ -1288,18 +1288,18 @@ let AddedComplexity = 20 in { } // zext i1->i64 -def: Pat<(i64 (zext (i1 PredRegs:$src1))), - (Zext64 (C2_muxii PredRegs:$src1, 1, 0))>; +def: Pat<(i64 (zext I1:$src1)), + (ToZext64 (C2_muxii PredRegs:$src1, 1, 0))>; // zext i32->i64 -def: Pat<(i64 (zext (i32 IntRegs:$src1))), - (Zext64 IntRegs:$src1)>; +def: Pat<(i64 (zext I32:$src1)), + (ToZext64 IntRegs:$src1)>; let AddedComplexity = 40 in multiclass T_StoreAbsReg_Pats { def : Pat<(stOp (VT RC:$src4), - (add (shl (i32 IntRegs:$src1), u2_0ImmPred:$src2), + (add (shl I32:$src1, u2_0ImmPred:$src2), u32_0ImmPred:$src3)), (MI IntRegs:$src1, u2_0ImmPred:$src2, u32_0ImmPred:$src3, RC:$src4)>; @@ -1319,8 +1319,8 @@ defm : T_StoreAbsReg_Pats ; defm : T_StoreAbsReg_Pats ; class Storexs_pat - : Pat<(Store Value:$Ru, (add (i32 IntRegs:$Rs), - (i32 (shl (i32 IntRegs:$Rt), u2_0ImmPred:$u2)))), + : Pat<(Store Value:$Ru, (add I32:$Rs, + (i32 (shl I32:$Rt, u2_0ImmPred:$u2)))), (MI IntRegs:$Rs, IntRegs:$Rt, imm:$u2, Value:$Ru)>; let AddedComplexity = 40 in { @@ -1476,39 +1476,39 @@ def: Pat<(HexagonAtGot I32:$got, I32:$addr, s30_2ImmPred:$off), def: Pat<(HexagonAtPcrel I32:$addr), (C4_addipc imm:$addr)>; -def: Pat<(i64 (and (i64 DoubleRegs:$Rs), (i64 (not (i64 DoubleRegs:$Rt))))), +def: Pat<(i64 (and I64:$Rs, (i64 (not I64:$Rt)))), (A4_andnp DoubleRegs:$Rs, DoubleRegs:$Rt)>; -def: Pat<(i64 (or (i64 DoubleRegs:$Rs), (i64 (not (i64 DoubleRegs:$Rt))))), +def: Pat<(i64 (or I64:$Rs, (i64 (not I64:$Rt)))), (A4_ornp DoubleRegs:$Rs, DoubleRegs:$Rt)>; -def: Pat<(add (i32 IntRegs:$Rs), (add (i32 IntRegs:$Ru), s32_0ImmPred:$s6)), +def: Pat<(add I32:$Rs, (add I32:$Ru, s32_0ImmPred:$s6)), (S4_addaddi IntRegs:$Rs, IntRegs:$Ru, imm:$s6)>; // Rd=add(Rs,sub(#s6,Ru)) -def: Pat<(add (i32 IntRegs:$src1), (sub s32_0ImmPred:$src2, - (i32 IntRegs:$src3))), +def: Pat<(add I32:$src1, (sub s32_0ImmPred:$src2, + I32:$src3)), (S4_subaddi IntRegs:$src1, s32_0ImmPred:$src2, IntRegs:$src3)>; // Rd=sub(add(Rs,#s6),Ru) -def: Pat<(sub (add (i32 IntRegs:$src1), s32_0ImmPred:$src2), - (i32 IntRegs:$src3)), +def: Pat<(sub (add I32:$src1, s32_0ImmPred:$src2), + I32:$src3), (S4_subaddi IntRegs:$src1, s32_0ImmPred:$src2, IntRegs:$src3)>; // Rd=add(sub(Rs,Ru),#s6) -def: Pat<(add (sub (i32 IntRegs:$src1), (i32 IntRegs:$src3)), +def: Pat<(add (sub I32:$src1, I32:$src3), (s32_0ImmPred:$src2)), (S4_subaddi IntRegs:$src1, s32_0ImmPred:$src2, IntRegs:$src3)>; -def: Pat<(xor (i64 DoubleRegs:$dst2), - (xor (i64 DoubleRegs:$Rss), (i64 DoubleRegs:$Rtt))), +def: Pat<(xor I64:$dst2, + (xor I64:$Rss, I64:$Rtt)), (M4_xor_xacc DoubleRegs:$dst2, DoubleRegs:$Rss, DoubleRegs:$Rtt)>; -def: Pat<(or (i32 IntRegs:$Ru), (and (i32 IntRegs:$_src_), s32_0ImmPred:$s10)), +def: Pat<(or I32:$Ru, (and (i32 IntRegs:$_src_), s32_0ImmPred:$s10)), (S4_or_andix IntRegs:$Ru, IntRegs:$_src_, imm:$s10)>; -def: Pat<(or (i32 IntRegs:$src1), (and (i32 IntRegs:$Rs), s32_0ImmPred:$s10)), +def: Pat<(or I32:$src1, (and I32:$Rs, s32_0ImmPred:$s10)), (S4_or_andi IntRegs:$src1, IntRegs:$Rs, imm:$s10)>; -def: Pat<(or (i32 IntRegs:$src1), (or (i32 IntRegs:$Rs), s32_0ImmPred:$s10)), +def: Pat<(or I32:$src1, (or I32:$Rs, s32_0ImmPred:$s10)), (S4_or_ori IntRegs:$src1, IntRegs:$Rs, imm:$s10)>; @@ -1520,29 +1520,29 @@ def: Pat<(i32 (trunc (cttz I64:$Rss))), (S2_ct0p I64:$Rss)>; def: Pat<(i32 (trunc (cttz (not I64:$Rss)))), (S2_ct1p I64:$Rss)>; // Define leading/trailing patterns that require zero-extensions to 64 bits. -def: Pat<(i64 (ctlz I64:$Rss)), (Zext64 (S2_cl0p I64:$Rss))>; -def: Pat<(i64 (cttz I64:$Rss)), (Zext64 (S2_ct0p I64:$Rss))>; -def: Pat<(i64 (ctlz (not I64:$Rss))), (Zext64 (S2_cl1p I64:$Rss))>; -def: Pat<(i64 (cttz (not I64:$Rss))), (Zext64 (S2_ct1p I64:$Rss))>; +def: Pat<(i64 (ctlz I64:$Rss)), (ToZext64 (S2_cl0p I64:$Rss))>; +def: Pat<(i64 (cttz I64:$Rss)), (ToZext64 (S2_ct0p I64:$Rss))>; +def: Pat<(i64 (ctlz (not I64:$Rss))), (ToZext64 (S2_cl1p I64:$Rss))>; +def: Pat<(i64 (cttz (not I64:$Rss))), (ToZext64 (S2_ct1p I64:$Rss))>; let AddedComplexity = 20 in { // Complexity greater than cmp reg-imm. - def: Pat<(i1 (seteq (and (shl 1, u5_0ImmPred:$u5), (i32 IntRegs:$Rs)), 0)), - (S4_ntstbit_i (i32 IntRegs:$Rs), u5_0ImmPred:$u5)>; - def: Pat<(i1 (seteq (and (shl 1, (i32 IntRegs:$Rt)), (i32 IntRegs:$Rs)), 0)), - (S4_ntstbit_r (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))>; + def: Pat<(i1 (seteq (and (shl 1, u5_0ImmPred:$u5), I32:$Rs), 0)), + (S4_ntstbit_i I32:$Rs, u5_0ImmPred:$u5)>; + def: Pat<(i1 (seteq (and (shl 1, I32:$Rt), I32:$Rs), 0)), + (S4_ntstbit_r I32:$Rs, I32:$Rt)>; } // Add extra complexity to prefer these instructions over bitsset/bitsclr. // The reason is that tstbit/ntstbit can be folded into a compound instruction: // if ([!]tstbit(...)) jump ... let AddedComplexity = 100 in -def: Pat<(i1 (setne (and (i32 IntRegs:$Rs), (i32 Set5ImmPred:$u5)), (i32 0))), - (S2_tstbit_i (i32 IntRegs:$Rs), (BITPOS32 Set5ImmPred:$u5))>; +def: Pat<(i1 (setne (and I32:$Rs, (i32 Set5ImmPred:$u5)), (i32 0))), + (S2_tstbit_i I32:$Rs, (BITPOS32 Set5ImmPred:$u5))>; let AddedComplexity = 100 in -def: Pat<(i1 (seteq (and (i32 IntRegs:$Rs), (i32 Set5ImmPred:$u5)), (i32 0))), - (S4_ntstbit_i (i32 IntRegs:$Rs), (BITPOS32 Set5ImmPred:$u5))>; +def: Pat<(i1 (seteq (and I32:$Rs, (i32 Set5ImmPred:$u5)), (i32 0))), + (S4_ntstbit_i I32:$Rs, (BITPOS32 Set5ImmPred:$u5))>; // Do not increase complexity of these patterns. In the DAG, "cmp i8" may be // represented as a compare against "value & 0xFF", which is an exact match @@ -1558,17 +1558,17 @@ def: Pat<(i1 (setne (and I32:$Rs, I32:$Rt), I32:$Rt)), (C4_nbitsset I32:$Rs, I32:$Rt)>; -def: Pat<(add (mul (i32 IntRegs:$Rs), u6_0ImmPred:$U6), u32_0ImmPred:$u6), +def: Pat<(add (mul I32:$Rs, u6_0ImmPred:$U6), u32_0ImmPred:$u6), (M4_mpyri_addi imm:$u6, IntRegs:$Rs, imm:$U6)>; -def: Pat<(add (mul (i32 IntRegs:$Rs), (i32 IntRegs:$Rt)), u32_0ImmPred:$u6), +def: Pat<(add (mul I32:$Rs, I32:$Rt), u32_0ImmPred:$u6), (M4_mpyrr_addi imm:$u6, IntRegs:$Rs, IntRegs:$Rt)>; -def: Pat<(add (i32 IntRegs:$src1), (mul (i32 IntRegs:$src3), u6_2ImmPred:$src2)), +def: Pat<(add I32:$src1, (mul I32:$src3, u6_2ImmPred:$src2)), (M4_mpyri_addr_u2 IntRegs:$src1, imm:$src2, IntRegs:$src3)>; -def: Pat<(add (i32 IntRegs:$src1), (mul (i32 IntRegs:$src3), u32_0ImmPred:$src2)), +def: Pat<(add I32:$src1, (mul I32:$src3, u32_0ImmPred:$src2)), (M4_mpyri_addr IntRegs:$src1, IntRegs:$src3, imm:$src2)>; -def: Pat<(add (i32 IntRegs:$Ru), (mul (i32 IntRegs:$_src_), (i32 IntRegs:$Rs))), +def: Pat<(add I32:$Ru, (mul (i32 IntRegs:$_src_), I32:$Rs)), (M4_mpyrr_addr IntRegs:$Ru, IntRegs:$_src_, IntRegs:$Rs)>; def: T_vcmp_pat; @@ -1607,7 +1607,7 @@ let AddedComplexity = 200 in { (S4_subi_lsr_ri addrga:$addr, IntRegs:$src2, u5_0ImmPred:$src3)>; } -def: Pat<(shl s6_0ImmPred:$s6, (i32 IntRegs:$Rt)), +def: Pat<(shl s6_0ImmPred:$s6, I32:$Rt), (S4_lsli imm:$s6, IntRegs:$Rt)>; @@ -1915,11 +1915,11 @@ def : T_CMP_pat ; def : T_CMP_pat ; // Map cmplt(Rs, Imm) -> !cmpgt(Rs, Imm-1). -def: Pat<(i1 (setlt (i32 IntRegs:$src1), s32_0ImmPred:$src2)), +def: Pat<(i1 (setlt I32:$src1, s32_0ImmPred:$src2)), (C4_cmpltei IntRegs:$src1, (DEC_CONST_SIGNED s32_0ImmPred:$src2))>; // rs != rt -> !(rs == rt). -def: Pat<(i1 (setne (i32 IntRegs:$src1), s32_0ImmPred:$src2)), +def: Pat<(i1 (setne I32:$src1, s32_0ImmPred:$src2)), (C4_cmpneqi IntRegs:$src1, s32_0ImmPred:$src2)>; // SDNode for converting immediate C to C-1. @@ -1946,7 +1946,7 @@ def DEC_CONST_BYTE : SDNodeXForm; + (ToZext64 (PS_loadrubabs tglobaladdr:$absaddr))>; def: Loada_pat; def: Loada_pat; @@ -2104,17 +2104,17 @@ let AddedComplexity = 100 in { // We need a complexity of 120 here to override preceding handling of // zextload. let AddedComplexity = 120 in { - def: Loadam_pat; - def: Loadam_pat; - def: Loadam_pat; + def: Loadam_pat; + def: Loadam_pat; + def: Loadam_pat; - def: Loadam_pat; - def: Loadam_pat; - def: Loadam_pat; + def: Loadam_pat; + def: Loadam_pat; + def: Loadam_pat; - def: Loadam_pat; - def: Loadam_pat; - def: Loadam_pat; + def: Loadam_pat; + def: Loadam_pat; + def: Loadam_pat; } let AddedComplexity = 100 in { @@ -2147,12 +2147,12 @@ def: Storea_pat, I32, addrgp, PS_storerhabs>; def: Storea_pat, I32, addrgp, PS_storeriabs>; def: Storea_pat, I64, addrgp, PS_storerdabs>; -def: Pat<(or (or (or (shl (i64 (zext (i32 (and (i32 IntRegs:$b), (i32 65535))))), +def: Pat<(or (or (or (shl (i64 (zext (i32 (and I32:$b, (i32 65535))))), (i32 16)), - (i64 (zext (i32 (and (i32 IntRegs:$a), (i32 65535)))))), - (shl (i64 (anyext (i32 (and (i32 IntRegs:$c), (i32 65535))))), + (i64 (zext (i32 (and I32:$a, (i32 65535)))))), + (shl (i64 (anyext (i32 (and I32:$c, (i32 65535))))), (i32 32))), - (shl (i64 (anyext (i32 IntRegs:$d))), (i32 48))), + (shl (i64 (anyext I32:$d)), (i32 48))), (Insert4 IntRegs:$a, IntRegs:$b, IntRegs:$c, IntRegs:$d)>; // We need custom lowering of ISD::PREFETCH into HexagonISD::DCFETCH @@ -2629,12 +2629,12 @@ def: Pat<(i32 (fp_to_sint F64:$src1)), (LoReg (F2_conv_df2d_chop F64:$src1))>, Requires<[HasV5T]>; -def : Pat <(fabs (f32 IntRegs:$src1)), - (S2_clrbit_i (f32 IntRegs:$src1), 31)>, +def : Pat <(fabs F32:$src1), + (S2_clrbit_i F32:$src1, 31)>, Requires<[HasV5T]>; -def : Pat <(fneg (f32 IntRegs:$src1)), - (S2_togglebit_i (f32 IntRegs:$src1), 31)>, +def : Pat <(fneg F32:$src1), + (S2_togglebit_i F32:$src1, 31)>, Requires<[HasV5T]>; @@ -3056,20 +3056,20 @@ def: Pat<(add V2I32:$Rx, (mul V2I32:$Rs, V2I32:$Rt)), // Adds two v4i8: Hexagon does not have an insn for this one, so we // use the double add v8i8, and use only the low part of the result. def: Pat<(v4i8 (add (v4i8 IntRegs:$Rs), (v4i8 IntRegs:$Rt))), - (LoReg (A2_vaddub (Zext64 $Rs), (Zext64 $Rt)))>; + (LoReg (A2_vaddub (ToZext64 $Rs), (ToZext64 $Rt)))>; // Subtract two v4i8: Hexagon does not have an insn for this one, so we // use the double sub v8i8, and use only the low part of the result. def: Pat<(v4i8 (sub (v4i8 IntRegs:$Rs), (v4i8 IntRegs:$Rt))), - (LoReg (A2_vsubub (Zext64 $Rs), (Zext64 $Rt)))>; + (LoReg (A2_vsubub (ToZext64 $Rs), (ToZext64 $Rt)))>; // // No 32 bit vector mux. // def: Pat<(v4i8 (select I1:$Pu, V4I8:$Rs, V4I8:$Rt)), - (LoReg (C2_vmux I1:$Pu, (Zext64 $Rs), (Zext64 $Rt)))>; + (LoReg (C2_vmux I1:$Pu, (ToZext64 $Rs), (ToZext64 $Rt)))>; def: Pat<(v2i16 (select I1:$Pu, V2I16:$Rs, V2I16:$Rt)), - (LoReg (C2_vmux I1:$Pu, (Zext64 $Rs), (Zext64 $Rt)))>; + (LoReg (C2_vmux I1:$Pu, (ToZext64 $Rs), (ToZext64 $Rt)))>; // // 64-bit vector mux. @@ -3085,18 +3085,18 @@ def: Pat<(v2i32 (vselect V2I1:$Pu, V2I32:$Rs, V2I32:$Rt)), // No 32 bit vector compare. // def: Pat<(i1 (seteq V4I8:$Rs, V4I8:$Rt)), - (A2_vcmpbeq (Zext64 $Rs), (Zext64 $Rt))>; + (A2_vcmpbeq (ToZext64 $Rs), (ToZext64 $Rt))>; def: Pat<(i1 (setgt V4I8:$Rs, V4I8:$Rt)), - (A4_vcmpbgt (Zext64 $Rs), (Zext64 $Rt))>; + (A4_vcmpbgt (ToZext64 $Rs), (ToZext64 $Rt))>; def: Pat<(i1 (setugt V4I8:$Rs, V4I8:$Rt)), - (A2_vcmpbgtu (Zext64 $Rs), (Zext64 $Rt))>; + (A2_vcmpbgtu (ToZext64 $Rs), (ToZext64 $Rt))>; def: Pat<(i1 (seteq V2I16:$Rs, V2I16:$Rt)), - (A2_vcmpheq (Zext64 $Rs), (Zext64 $Rt))>; + (A2_vcmpheq (ToZext64 $Rs), (ToZext64 $Rt))>; def: Pat<(i1 (setgt V2I16:$Rs, V2I16:$Rt)), - (A2_vcmphgt (Zext64 $Rs), (Zext64 $Rt))>; + (A2_vcmphgt (ToZext64 $Rs), (ToZext64 $Rt))>; def: Pat<(i1 (setugt V2I16:$Rs, V2I16:$Rt)), - (A2_vcmphgtu (Zext64 $Rs), (Zext64 $Rt))>; + (A2_vcmphgtu (ToZext64 $Rs), (ToZext64 $Rt))>; class InvertCmp_pat