From 789bf2ab8bbea231d5bef3314abcf6be50ad4129 Mon Sep 17 00:00:00 2001 From: Evandro Menezes Date: Fri, 8 Dec 2017 21:09:59 +0000 Subject: [PATCH] [AArch64] Add Exynos to host detection Differential revision: https://reviews.llvm.org/D40985 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320195 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Support/Host.cpp | 31 +++++++++++++++++++++++++++++++ unittests/Support/Host.cpp | 31 +++++++++++++++++++++++++++++++ 2 files changed, 62 insertions(+) diff --git a/lib/Support/Host.cpp b/lib/Support/Host.cpp index e307335f8bb..fac58ab365d 100644 --- a/lib/Support/Host.cpp +++ b/lib/Support/Host.cpp @@ -216,6 +216,37 @@ StringRef sys::detail::getHostCPUNameForARM( .Case("0xc01", "saphira") .Default("generic"); + if (Implementer == "0x53") { // Samsung Electronics Co., Ltd. + // The Exynos chips have a convoluted ID scheme that doesn't seem to follow + // any predictive pattern across variants and parts. + unsigned Variant = 0, Part = 0; + + // Look for the CPU variant line, whose value is a 1 digit hexadecimal + // number, corresponding to the Variant bits in the CP15/C0 register. + for (auto I : Lines) + if (I.consume_front("CPU variant")) + I.ltrim("\t :").getAsInteger(0, Variant); + + // Look for the CPU part line, whose value is a 3 digit hexadecimal + // number, corresponding to the PartNum bits in the CP15/C0 register. + for (auto I : Lines) + if (I.consume_front("CPU part")) + I.ltrim("\t :").getAsInteger(0, Part); + + unsigned Exynos = (Variant << 12) | Part; + switch (Exynos) { + default: + // Default by falling through to Exynos M1. + LLVM_FALLTHROUGH; + + case 0x1001: + return "exynos-m1"; + + case 0x4001: + return "exynos-m2"; + } + } + return "generic"; } diff --git a/unittests/Support/Host.cpp b/unittests/Support/Host.cpp index 23200fdbbc7..736b04c2049 100644 --- a/unittests/Support/Host.cpp +++ b/unittests/Support/Host.cpp @@ -139,6 +139,37 @@ Hardware : Qualcomm Technologies, Inc MSM8992 EXPECT_EQ(sys::detail::getHostCPUNameForARM(MSM8992ProcCpuInfo), "cortex-a53"); + + // Exynos big.LITTLE weirdness + const std::string ExynosProcCpuInfo = R"( +processor : 0 +Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 +CPU implementer : 0x41 +CPU architecture: 8 +CPU variant : 0x0 +CPU part : 0xd03 + +processor : 1 +Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 +CPU implementer : 0x53 +CPU architecture: 8 +)"; + + // Verify default for Exynos. + EXPECT_EQ(sys::detail::getHostCPUNameForARM(ExynosProcCpuInfo + + "CPU variant : 0xc\n" + "CPU part : 0xafe"), + "exynos-m1"); + // Verify Exynos M1. + EXPECT_EQ(sys::detail::getHostCPUNameForARM(ExynosProcCpuInfo + + "CPU variant : 0x1\n" + "CPU part : 0x001"), + "exynos-m1"); + // Verify Exynos M2. + EXPECT_EQ(sys::detail::getHostCPUNameForARM(ExynosProcCpuInfo + + "CPU variant : 0x4\n" + "CPU part : 0x001"), + "exynos-m2"); } #if defined(__APPLE__) -- 2.50.1