From 7863128a7deac7f5c52fae553305578fd2ee72f7 Mon Sep 17 00:00:00 2001 From: Sam Parker Date: Mon, 18 Sep 2017 14:28:51 +0000 Subject: [PATCH] [ARM] Implement isTruncateFree Implement the isTruncateFree hooks, lifted from AArch64, that are used by TargetTransformInfo. This allows simplifycfg to reduce the test case into a single basic block. Differential Revision: https://reviews.llvm.org/D37516 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313533 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARMISelLowering.cpp | 20 +++++++++++++++ lib/Target/ARM/ARMISelLowering.h | 3 ++- .../SimplifyCFG/ARM/select-trunc-i64.ll | 25 +++++++++++++++++++ 3 files changed, 47 insertions(+), 1 deletion(-) create mode 100644 test/Transforms/SimplifyCFG/ARM/select-trunc-i64.ll diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index e947ddc7031..02fbb1e811d 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -12179,6 +12179,26 @@ EVT ARMTargetLowering::getOptimalMemOpType(uint64_t Size, return MVT::Other; } +// 64-bit integers are split into their high and low parts and held in two +// different registers, so the trunc is free since the low register can just +// be used. +bool ARMTargetLowering::isTruncateFree(Type *SrcTy, Type *DstTy) const { + if (!SrcTy->isIntegerTy() || !DstTy->isIntegerTy()) + return false; + unsigned NumBits1 = SrcTy->getPrimitiveSizeInBits(); + unsigned NumBits2 = DstTy->getPrimitiveSizeInBits(); + return NumBits1 > NumBits2; +} + +bool ARMTargetLowering::isTruncateFree(EVT SrcVT, EVT DstVT) const { + if (SrcVT.isVector() || DstVT.isVector() || !SrcVT.isInteger() || + !DstVT.isInteger()) + return false; + unsigned NumBits1 = SrcVT.getSizeInBits(); + unsigned NumBits2 = DstVT.getSizeInBits(); + return NumBits1 > NumBits2; +} + bool ARMTargetLowering::isZExtFree(SDValue Val, EVT VT2) const { if (Val.getOpcode() != ISD::LOAD) return false; diff --git a/lib/Target/ARM/ARMISelLowering.h b/lib/Target/ARM/ARMISelLowering.h index 40cf54586af..4836569919a 100644 --- a/lib/Target/ARM/ARMISelLowering.h +++ b/lib/Target/ARM/ARMISelLowering.h @@ -308,7 +308,8 @@ class InstrItineraryData; bool MemcpyStrSrc, MachineFunction &MF) const override; - using TargetLowering::isZExtFree; + bool isTruncateFree(Type *SrcTy, Type *DstTy) const override; + bool isTruncateFree(EVT SrcVT, EVT DstVT) const override; bool isZExtFree(SDValue Val, EVT VT2) const override; bool isVectorLoadExtDesirable(SDValue ExtVal) const override; diff --git a/test/Transforms/SimplifyCFG/ARM/select-trunc-i64.ll b/test/Transforms/SimplifyCFG/ARM/select-trunc-i64.ll new file mode 100644 index 00000000000..9484de77db4 --- /dev/null +++ b/test/Transforms/SimplifyCFG/ARM/select-trunc-i64.ll @@ -0,0 +1,25 @@ +;RUN: opt -S -simplifycfg -mtriple=arm < %s | FileCheck %s +target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" + +; CHECK-LABEL: select_trunc_i64 +; CHECK-NOT: br +; CHECK: select +; CHECK: select +define arm_aapcscc i32 @select_trunc_i64(i32 %a, i32 %b) { +entry: + %conv = sext i32 %a to i64 + %conv1 = sext i32 %b to i64 + %add = add nsw i64 %conv1, %conv + %cmp = icmp sgt i64 %add, 2147483647 + br i1 %cmp, label %cond.end7, label %cond.false + +cond.false: ; preds = %entry + %0 = icmp sgt i64 %add, -2147483648 + %cond = select i1 %0, i64 %add, i64 -2147483648 + %extract.t = trunc i64 %cond to i32 + br label %cond.end7 + +cond.end7: ; preds = %cond.false, %entry + %cond8.off0 = phi i32 [ 2147483647, %entry ], [ %extract.t, %cond.false ] + ret i32 %cond8.off0 +} -- 2.50.1