From 780569c04a0fc5441ee5218c8f3620a51d19edfa Mon Sep 17 00:00:00 2001 From: Ivan Grokhotkov Date: Mon, 10 Jul 2017 16:36:56 +0800 Subject: [PATCH] esp32: fix RTC watchdog configuration in esp_restart MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit RTC watchdog didn’t have any actions configured for any of the stages. This change configures it to use SW_SYSTEM_RESET at stage 0 and a full reset at stage 1. The timeout is now calculated based on RTC_SLOW_CLK frequency. --- components/esp32/system_api.c | 6 ++++-- components/soc/esp32/include/soc/rtc_cntl_reg.h | 1 + 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/components/esp32/system_api.c b/components/esp32/system_api.c index c79761fd7d..29a050bf9a 100644 --- a/components/esp32/system_api.c +++ b/components/esp32/system_api.c @@ -264,13 +264,15 @@ void IRAM_ATTR esp_restart_noos() esp_dport_access_int_deinit(); // We need to disable TG0/TG1 watchdogs - // First enable RTC watchdog to be on the safe side + // First enable RTC watchdog for 1 second REG_WRITE(RTC_CNTL_WDTWPROTECT_REG, RTC_CNTL_WDT_WKEY_VALUE); REG_WRITE(RTC_CNTL_WDTCONFIG0_REG, RTC_CNTL_WDT_FLASHBOOT_MOD_EN_M | + (RTC_WDT_STG_SEL_RESET_SYSTEM << RTC_CNTL_WDT_STG0_S) | + (RTC_WDT_STG_SEL_RESET_RTC << RTC_CNTL_WDT_STG1_S) | (1 << RTC_CNTL_WDT_SYS_RESET_LENGTH_S) | (1 << RTC_CNTL_WDT_CPU_RESET_LENGTH_S) ); - REG_WRITE(RTC_CNTL_WDTCONFIG1_REG, 128000); + REG_WRITE(RTC_CNTL_WDTCONFIG1_REG, rtc_clk_slow_freq_get_hz() * 1); // Disable TG0/TG1 watchdogs TIMERG0.wdt_wprotect=TIMG_WDT_WKEY_VALUE; diff --git a/components/soc/esp32/include/soc/rtc_cntl_reg.h b/components/soc/esp32/include/soc/rtc_cntl_reg.h index 02f8dff2c4..ffcbb3c033 100644 --- a/components/soc/esp32/include/soc/rtc_cntl_reg.h +++ b/components/soc/esp32/include/soc/rtc_cntl_reg.h @@ -1718,6 +1718,7 @@ #define RTC_WDT_STG_SEL_INT 1 #define RTC_WDT_STG_SEL_RESET_CPU 2 #define RTC_WDT_STG_SEL_RESET_SYSTEM 3 +#define RTC_WDT_STG_SEL_RESET_RTC 4 #define RTC_CNTL_WDTCONFIG1_REG (DR_REG_RTCCNTL_BASE + 0x90) /* RTC_CNTL_WDT_STG0_HOLD : R/W ;bitpos:[31:0] ;default: 32'd128000 ; */ -- 2.40.0