From 765a7627d9b524d7078c03464432bced5fb777b4 Mon Sep 17 00:00:00 2001 From: Andrea Di Biagio Date: Mon, 17 Dec 2018 14:27:33 +0000 Subject: [PATCH] [MCA] Add support for BeginGroup/EndGroup. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@349354 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/MCA/Instruction.h | 2 ++ lib/MCA/InstrBuilder.cpp | 2 ++ lib/MCA/Stages/DispatchStage.cpp | 8 ++++++++ test/tools/llvm-mca/SystemZ/stm-lm.s | 20 ++++++++++---------- 4 files changed, 22 insertions(+), 10 deletions(-) diff --git a/include/llvm/MCA/Instruction.h b/include/llvm/MCA/Instruction.h index d3fa8ccdc93..148651b22da 100644 --- a/include/llvm/MCA/Instruction.h +++ b/include/llvm/MCA/Instruction.h @@ -334,6 +334,8 @@ struct InstrDesc { bool MayLoad; bool MayStore; bool HasSideEffects; + bool BeginGroup; + bool EndGroup; // A zero latency instruction doesn't consume any scheduler resources. bool isZeroLatency() const { return !MaxLatency && Resources.empty(); } diff --git a/lib/MCA/InstrBuilder.cpp b/lib/MCA/InstrBuilder.cpp index cd3b815c3a6..8d501dc6b15 100644 --- a/lib/MCA/InstrBuilder.cpp +++ b/lib/MCA/InstrBuilder.cpp @@ -536,6 +536,8 @@ InstrBuilder::createInstrDescImpl(const MCInst &MCI) { ID->MayLoad = MCDesc.mayLoad(); ID->MayStore = MCDesc.mayStore(); ID->HasSideEffects = MCDesc.hasUnmodeledSideEffects(); + ID->BeginGroup = SCDesc.BeginGroup; + ID->EndGroup = SCDesc.EndGroup; initializeUsedResources(*ID, SCDesc, STI, ProcResourceMasks); computeMaxLatency(*ID, MCDesc, SCDesc, STI); diff --git a/lib/MCA/Stages/DispatchStage.cpp b/lib/MCA/Stages/DispatchStage.cpp index 52e04fad58e..7fb4eb6a1c0 100644 --- a/lib/MCA/Stages/DispatchStage.cpp +++ b/lib/MCA/Stages/DispatchStage.cpp @@ -99,6 +99,10 @@ Error DispatchStage::dispatch(InstRef IR) { AvailableEntries -= NumMicroOps; } + // Check if this instructions ends the dispatch group. + if (Desc.EndGroup) + AvailableEntries = 0; + // Check if this is an optimizable reg-reg move. bool IsEliminated = false; if (IS.isOptimizableMove()) { @@ -164,6 +168,10 @@ bool DispatchStage::isAvailable(const InstRef &IR) const { unsigned Required = std::min(Desc.NumMicroOps, DispatchWidth); if (Required > AvailableEntries) return false; + + if (Desc.BeginGroup && AvailableEntries != DispatchWidth) + return false; + // The dispatch logic doesn't internally buffer instructions. It only accepts // instructions that can be successfully moved to the next stage during this // same cycle. diff --git a/test/tools/llvm-mca/SystemZ/stm-lm.s b/test/tools/llvm-mca/SystemZ/stm-lm.s index 5118635fff9..db2d79663d4 100644 --- a/test/tools/llvm-mca/SystemZ/stm-lm.s +++ b/test/tools/llvm-mca/SystemZ/stm-lm.s @@ -6,7 +6,7 @@ lmg %r6, %r15, 48(%r15) # CHECK: Iterations: 100 # CHECK-NEXT: Instructions: 200 -# CHECK-NEXT: Total Cycles: 1003 +# CHECK-NEXT: Total Cycles: 1004 # CHECK-NEXT: Total uOps: 600 # CHECK: Dispatch Width: 6 @@ -51,15 +51,15 @@ lmg %r6, %r15, 48(%r15) # CHECK-NEXT: - - - - 0.10 4.90 - - - - - - - lmg %r6, %r15, 48(%r15) # CHECK: Timeline view: -# CHECK-NEXT: 0123456789 012 +# CHECK-NEXT: 0123456789 0123 # CHECK-NEXT: Index 0123456789 0123456789 -# CHECK: [0,0] DeER . . . . . . . stmg %r6, %r15, 48(%r15) -# CHECK-NEXT: [0,1] DeeeeeeeeeeER . . . . . lmg %r6, %r15, 48(%r15) -# CHECK-NEXT: [1,0] .D=========eER . . . . . stmg %r6, %r15, 48(%r15) -# CHECK-NEXT: [1,1] .D=========eeeeeeeeeeER . . . lmg %r6, %r15, 48(%r15) -# CHECK-NEXT: [2,0] . D==================eER . . . stmg %r6, %r15, 48(%r15) -# CHECK-NEXT: [2,1] . D==================eeeeeeeeeeER lmg %r6, %r15, 48(%r15) +# CHECK: [0,0] DeER . . . . . . . stmg %r6, %r15, 48(%r15) +# CHECK-NEXT: [0,1] .DeeeeeeeeeeER . . . . . lmg %r6, %r15, 48(%r15) +# CHECK-NEXT: [1,0] . D=========eER. . . . . stmg %r6, %r15, 48(%r15) +# CHECK-NEXT: [1,1] . D========eeeeeeeeeeER . . . lmg %r6, %r15, 48(%r15) +# CHECK-NEXT: [2,0] . D=================eER. . . stmg %r6, %r15, 48(%r15) +# CHECK-NEXT: [2,1] . D================eeeeeeeeeeER lmg %r6, %r15, 48(%r15) # CHECK: Average Wait times (based on the timeline view): # CHECK-NEXT: [0]: Executions @@ -68,5 +68,5 @@ lmg %r6, %r15, 48(%r15) # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage # CHECK: [0] [1] [2] [3] -# CHECK-NEXT: 0. 3 10.0 0.3 0.0 stmg %r6, %r15, 48(%r15) -# CHECK-NEXT: 1. 3 10.0 0.3 0.0 lmg %r6, %r15, 48(%r15) +# CHECK-NEXT: 0. 3 9.7 0.3 0.0 stmg %r6, %r15, 48(%r15) +# CHECK-NEXT: 1. 3 9.0 0.3 0.0 lmg %r6, %r15, 48(%r15) -- 2.50.1