From 75134ec4826e303bd5e6e517fce6b973e426b00d Mon Sep 17 00:00:00 2001 From: Eugene Zelenko Date: Thu, 10 Aug 2017 00:46:15 +0000 Subject: [PATCH] [AMDGPU] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310541 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/AMDGPU/AMDGPUUnifyMetadata.cpp | 9 ++-- .../AMDGPU/AsmParser/AMDGPUAsmParser.cpp | 40 +++++++------- .../Disassembler/AMDGPUDisassembler.cpp | 41 +++++++++----- .../AMDGPU/Disassembler/AMDGPUDisassembler.h | 8 ++- lib/Target/AMDGPU/GCNIterativeScheduler.cpp | 53 ++++++++++++++----- lib/Target/AMDGPU/GCNIterativeScheduler.h | 27 ++++++---- lib/Target/AMDGPU/GCNRegPressure.cpp | 25 ++++++--- lib/Target/AMDGPU/GCNRegPressure.h | 29 ++++++---- .../AMDGPU/R600ControlFlowFinalizer.cpp | 12 +++-- lib/Target/AMDGPU/R600ExpandSpecialInstrs.cpp | 20 ++++--- .../AMDGPU/R600OptimizeVectorRegisters.cpp | 21 ++++---- lib/Target/AMDGPU/SIMemoryLegalizer.cpp | 28 ++++++++-- .../AMDGPU/Utils/AMDKernelCodeTUtils.cpp | 27 +++++----- lib/Target/AMDGPU/Utils/AMDKernelCodeTUtils.h | 29 +++++----- 14 files changed, 227 insertions(+), 142 deletions(-) diff --git a/lib/Target/AMDGPU/AMDGPUUnifyMetadata.cpp b/lib/Target/AMDGPU/AMDGPUUnifyMetadata.cpp index 3a0c3ede08f..b78568e89cf 100644 --- a/lib/Target/AMDGPU/AMDGPUUnifyMetadata.cpp +++ b/lib/Target/AMDGPU/AMDGPUUnifyMetadata.cpp @@ -1,4 +1,4 @@ -//===-- AMDGPUUnifyMetadata.cpp - Unify OpenCL metadata -------------------===// +//===- AMDGPUUnifyMetadata.cpp - Unify OpenCL metadata --------------------===// // // The LLVM Compiler Infrastructure // @@ -16,7 +16,7 @@ #include "llvm/ADT/SmallVector.h" #include "llvm/ADT/StringRef.h" #include "llvm/IR/Constants.h" -#include "llvm/IR/Function.h" +#include "llvm/IR/Metadata.h" #include "llvm/IR/Module.h" #include "llvm/Pass.h" #include @@ -41,10 +41,11 @@ namespace { class AMDGPUUnifyMetadata : public ModulePass { public: static char ID; - explicit AMDGPUUnifyMetadata() : ModulePass(ID) {}; + + explicit AMDGPUUnifyMetadata() : ModulePass(ID) {} private: - virtual bool runOnModule(Module &M); + bool runOnModule(Module &M) override; /// \brief Unify version metadata. /// \return true if changes are made. diff --git a/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp index 17e7288ac3a..9a0e4a39d31 100644 --- a/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp +++ b/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp @@ -1,4 +1,4 @@ -//===-- AMDGPUAsmParser.cpp - Parse SI asm to MCInst instructions ---------===// +//===- AMDGPUAsmParser.cpp - Parse SI asm to MCInst instructions ----------===// // // The LLVM Compiler Infrastructure // @@ -7,6 +7,7 @@ // //===----------------------------------------------------------------------===// +#include "AMDGPU.h" #include "AMDKernelCodeT.h" #include "MCTargetDesc/AMDGPUMCTargetDesc.h" #include "MCTargetDesc/AMDGPUTargetStreamer.h" @@ -40,7 +41,9 @@ #include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCSubtargetInfo.h" #include "llvm/MC/MCSymbol.h" +#include "llvm/Support/AMDGPUCodeObjectMetadata.h" #include "llvm/Support/Casting.h" +#include "llvm/Support/Compiler.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/MathExtras.h" #include "llvm/Support/SMLoc.h" @@ -83,7 +86,7 @@ public: AMDGPUOperand(KindTy Kind_, const AMDGPUAsmParser *AsmParser_) : MCParsedAsmOperand(), Kind(Kind_), AsmParser(AsmParser_) {} - typedef std::unique_ptr Ptr; + using Ptr = std::unique_ptr; struct Modifiers { bool Abs = false; @@ -846,7 +849,7 @@ public: Match_PreferE32 = FIRST_TARGET_MATCH_RESULT_TY }; - typedef std::map OptionalImmIndexMap; + using OptionalImmIndexMap = std::map; AMDGPUAsmParser(const MCSubtargetInfo &STI, MCAsmParser &_Parser, const MCInstrInfo &MII, @@ -994,8 +997,9 @@ public: private: struct OperandInfoTy { int64_t Id; - bool IsSymbolic; - OperandInfoTy(int64_t Id_) : Id(Id_), IsSymbolic(false) { } + bool IsSymbolic = false; + + OperandInfoTy(int64_t Id_) : Id(Id_) {} }; bool parseSendMsgConstruct(OperandInfoTy &Msg, OperandInfoTy &Operation, int64_t &StreamId); @@ -1285,7 +1289,6 @@ uint64_t AMDGPUOperand::applyInputFPModifiers(uint64_t Val, unsigned Size) const } void AMDGPUOperand::addImmOperands(MCInst &Inst, unsigned N, bool ApplyModifiers) const { - if (AMDGPU::isSISrcOperand(AsmParser->getMII()->get(Inst.getOpcode()), Inst.getNumOperands())) { addLiteralImmOperand(Inst, Imm.Val, @@ -1317,7 +1320,7 @@ void AMDGPUOperand::addLiteralImmOperand(MCInst &Inst, int64_t Val, bool ApplyMo case AMDGPU::OPERAND_REG_IMM_INT64: case AMDGPU::OPERAND_REG_IMM_FP64: case AMDGPU::OPERAND_REG_INLINE_C_INT64: - case AMDGPU::OPERAND_REG_INLINE_C_FP64: { + case AMDGPU::OPERAND_REG_INLINE_C_FP64: if (AMDGPU::isInlinableLiteral64(Literal.getZExtValue(), AsmParser->hasInv2PiInlineImm())) { Inst.addOperand(MCOperand::createImm(Literal.getZExtValue())); @@ -1341,7 +1344,7 @@ void AMDGPUOperand::addLiteralImmOperand(MCInst &Inst, int64_t Val, bool ApplyMo // unclear how we should encode them. This case should be checked earlier // in predicate methods (isLiteralImm()) llvm_unreachable("fp literal in 64-bit integer instruction."); - } + case AMDGPU::OPERAND_REG_IMM_INT32: case AMDGPU::OPERAND_REG_IMM_FP32: case AMDGPU::OPERAND_REG_INLINE_C_INT32: @@ -1383,7 +1386,7 @@ void AMDGPUOperand::addLiteralImmOperand(MCInst &Inst, int64_t Val, bool ApplyMo case AMDGPU::OPERAND_REG_IMM_INT32: case AMDGPU::OPERAND_REG_IMM_FP32: case AMDGPU::OPERAND_REG_INLINE_C_INT32: - case AMDGPU::OPERAND_REG_INLINE_C_FP32: { + case AMDGPU::OPERAND_REG_INLINE_C_FP32: if (isInt<32>(Val) && AMDGPU::isInlinableLiteral32(static_cast(Val), AsmParser->hasInv2PiInlineImm())) { @@ -1393,11 +1396,11 @@ void AMDGPUOperand::addLiteralImmOperand(MCInst &Inst, int64_t Val, bool ApplyMo Inst.addOperand(MCOperand::createImm(Val & 0xffffffff)); return; - } + case AMDGPU::OPERAND_REG_IMM_INT64: case AMDGPU::OPERAND_REG_IMM_FP64: case AMDGPU::OPERAND_REG_INLINE_C_INT64: - case AMDGPU::OPERAND_REG_INLINE_C_FP64: { + case AMDGPU::OPERAND_REG_INLINE_C_FP64: if (AMDGPU::isInlinableLiteral64(Val, AsmParser->hasInv2PiInlineImm())) { Inst.addOperand(MCOperand::createImm(Val)); return; @@ -1405,11 +1408,11 @@ void AMDGPUOperand::addLiteralImmOperand(MCInst &Inst, int64_t Val, bool ApplyMo Inst.addOperand(MCOperand::createImm(Lo_32(Val))); return; - } + case AMDGPU::OPERAND_REG_IMM_INT16: case AMDGPU::OPERAND_REG_IMM_FP16: case AMDGPU::OPERAND_REG_INLINE_C_INT16: - case AMDGPU::OPERAND_REG_INLINE_C_FP16: { + case AMDGPU::OPERAND_REG_INLINE_C_FP16: if (isInt<16>(Val) && AMDGPU::isInlinableLiteral16(static_cast(Val), AsmParser->hasInv2PiInlineImm())) { @@ -1419,7 +1422,7 @@ void AMDGPUOperand::addLiteralImmOperand(MCInst &Inst, int64_t Val, bool ApplyMo Inst.addOperand(MCOperand::createImm(Val & 0xffff)); return; - } + case AMDGPU::OPERAND_REG_INLINE_C_V2INT16: case AMDGPU::OPERAND_REG_INLINE_C_V2FP16: { auto LiteralVal = static_cast(Literal.getLoBits(16).getZExtValue()); @@ -1717,7 +1720,6 @@ AMDGPUAsmParser::parseAbsoluteExpr(int64_t &Val, bool AbsMod) { if (AbsMod && getLexer().peekTok().is(AsmToken::Pipe) && (getLexer().getKind() == AsmToken::Integer || getLexer().getKind() == AsmToken::Real)) { - // This is a workaround for handling operands like these: // |1.0| // |-1| @@ -2117,7 +2119,6 @@ bool AMDGPUAsmParser::validateConstantBusLimitations(const MCInst &Inst) { SIInstrFlags::VOP1 | SIInstrFlags::VOP2 | SIInstrFlags::VOP3 | SIInstrFlags::VOP3P | SIInstrFlags::SDWA)) { - // Check special imm operands (used by madmk, etc) if (AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::imm) != -1) { ++ConstantBusUseCount; @@ -2162,7 +2163,6 @@ bool AMDGPUAsmParser::validateConstantBusLimitations(const MCInst &Inst) { } bool AMDGPUAsmParser::validateEarlyClobberLimitations(const MCInst &Inst) { - const unsigned Opcode = Inst.getOpcode(); const MCInstrDesc &Desc = MII.get(Opcode); @@ -4128,8 +4128,8 @@ static bool isRegOrImmWithInputMods(const MCInstrDesc &Desc, unsigned OpNum) { && Desc.getOperandConstraint(OpNum + 1, MCOI::OperandConstraint::TIED_TO) == -1; } -void AMDGPUAsmParser::cvtVOP3Interp(MCInst &Inst, const OperandVector &Operands) { - +void AMDGPUAsmParser::cvtVOP3Interp(MCInst &Inst, const OperandVector &Operands) +{ OptionalImmIndexMap OptionalIdx; unsigned Opc = Inst.getOpcode(); @@ -4398,7 +4398,6 @@ AMDGPUAsmParser::parseDPPCtrl(OperandVector &Operands) { if (getLexer().isNot(AsmToken::RBrac)) return MatchOperand_ParseFail; Parser.Lex(); - } else { // sel:%d Parser.Lex(); @@ -4573,6 +4572,7 @@ void AMDGPUAsmParser::cvtSdwaVOPC(MCInst &Inst, const OperandVector &Operands) { void AMDGPUAsmParser::cvtSDWA(MCInst &Inst, const OperandVector &Operands, uint64_t BasicInstType, bool skipVcc) { using namespace llvm::AMDGPU::SDWA; + OptionalImmIndexMap OptionalIdx; bool skippedVcc = false; diff --git a/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp b/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp index 0433444a738..3fbdc847eda 100644 --- a/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp +++ b/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp @@ -1,4 +1,4 @@ -//===-- AMDGPUDisassembler.cpp - Disassembler for AMDGPU ISA --------------===// +//===- AMDGPUDisassembler.cpp - Disassembler for AMDGPU ISA ---------------===// // // The LLVM Compiler Infrastructure // @@ -17,29 +17,40 @@ // ToDo: What to do with instruction suffixes (v_mov_b32 vs v_mov_b32_e32)? -#include "AMDGPUDisassembler.h" +#include "Disassembler/AMDGPUDisassembler.h" #include "AMDGPU.h" #include "AMDGPURegisterInfo.h" -#include "MCTargetDesc/AMDGPUMCTargetDesc.h" #include "SIDefines.h" #include "Utils/AMDGPUBaseInfo.h" - +#include "llvm-c/Disassembler.h" +#include "llvm/ADT/APInt.h" +#include "llvm/ADT/ArrayRef.h" +#include "llvm/ADT/Twine.h" #include "llvm/BinaryFormat/ELF.h" #include "llvm/MC/MCContext.h" +#include "llvm/MC/MCDisassembler/MCDisassembler.h" +#include "llvm/MC/MCExpr.h" #include "llvm/MC/MCFixedLenDisassembler.h" #include "llvm/MC/MCInst.h" -#include "llvm/MC/MCInstrDesc.h" #include "llvm/MC/MCSubtargetInfo.h" -#include "llvm/Support/Debug.h" #include "llvm/Support/Endian.h" +#include "llvm/Support/ErrorHandling.h" +#include "llvm/Support/MathExtras.h" #include "llvm/Support/TargetRegistry.h" +#include "llvm/Support/raw_ostream.h" +#include +#include +#include +#include +#include +#include +#include using namespace llvm; #define DEBUG_TYPE "amdgpu-disassembler" -typedef llvm::MCDisassembler::DecodeStatus DecodeStatus; - +using DecodeStatus = llvm::MCDisassembler::DecodeStatus; inline static MCDisassembler::DecodeStatus addOperand(MCInst &Inst, const MCOperand& Opnd) { @@ -102,7 +113,6 @@ DECODE_OPERAND_REG(SReg_128) DECODE_OPERAND_REG(SReg_256) DECODE_OPERAND_REG(SReg_512) - static DecodeStatus decodeOperand_VSrc16(MCInst &Inst, unsigned Imm, uint64_t Addr, @@ -395,7 +405,6 @@ MCOperand AMDGPUDisassembler::decodeOperand_SReg_512(unsigned Val) const { return createSRegOperand(AMDGPU::SReg_512RegClassID, Val); } - MCOperand AMDGPUDisassembler::decodeLiteralConstant() const { // For now all literal constants are supposed to be unsigned integer // ToDo: deal with signed/unsigned 64-bit integer constants @@ -413,6 +422,7 @@ MCOperand AMDGPUDisassembler::decodeLiteralConstant() const { MCOperand AMDGPUDisassembler::decodeIntImmed(unsigned Imm) { using namespace AMDGPU::EncValues; + assert(Imm >= INLINE_INTEGER_C_MIN && Imm <= INLINE_INTEGER_C_MAX); return MCOperand::createImm((Imm <= INLINE_INTEGER_C_POSITIVE_MAX) ? (static_cast(Imm) - INLINE_INTEGER_C_MIN) : @@ -515,6 +525,7 @@ MCOperand AMDGPUDisassembler::decodeFPImmed(OpWidthTy Width, unsigned Imm) { unsigned AMDGPUDisassembler::getVgprClassId(const OpWidthTy Width) const { using namespace AMDGPU; + assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); switch (Width) { default: // fall @@ -529,6 +540,7 @@ unsigned AMDGPUDisassembler::getVgprClassId(const OpWidthTy Width) const { unsigned AMDGPUDisassembler::getSgprClassId(const OpWidthTy Width) const { using namespace AMDGPU; + assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); switch (Width) { default: // fall @@ -543,6 +555,7 @@ unsigned AMDGPUDisassembler::getSgprClassId(const OpWidthTy Width) const { unsigned AMDGPUDisassembler::getTtmpClassId(const OpWidthTy Width) const { using namespace AMDGPU; + assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); switch (Width) { default: // fall @@ -557,6 +570,7 @@ unsigned AMDGPUDisassembler::getTtmpClassId(const OpWidthTy Width) const { MCOperand AMDGPUDisassembler::decodeSrcOp(const OpWidthTy Width, unsigned Val) const { using namespace AMDGPU::EncValues; + assert(Val < 512); // enum9 if (VGPR_MIN <= Val && Val <= VGPR_MAX) { @@ -593,6 +607,7 @@ MCOperand AMDGPUDisassembler::decodeSrcOp(const OpWidthTy Width, unsigned Val) c MCOperand AMDGPUDisassembler::decodeSpecialReg32(unsigned Val) const { using namespace AMDGPU; + switch (Val) { case 102: return createRegOperand(getMCReg(FLAT_SCR_LO, STI)); case 103: return createRegOperand(getMCReg(FLAT_SCR_HI, STI)); @@ -625,6 +640,7 @@ MCOperand AMDGPUDisassembler::decodeSpecialReg32(unsigned Val) const { MCOperand AMDGPUDisassembler::decodeSpecialReg64(unsigned Val) const { using namespace AMDGPU; + switch (Val) { case 102: return createRegOperand(getMCReg(FLAT_SCR, STI)); case 106: return createRegOperand(VCC); @@ -669,7 +685,6 @@ MCOperand AMDGPUDisassembler::decodeSDWASrc32(unsigned Val) const { return decodeSDWASrc(OPW32, Val); } - MCOperand AMDGPUDisassembler::decodeSDWAVopcDst(unsigned Val) const { using namespace AMDGPU::SDWA; @@ -696,8 +711,8 @@ bool AMDGPUSymbolizer::tryAddingSymbolicOperand(MCInst &Inst, raw_ostream &/*cStream*/, int64_t Value, uint64_t /*Address*/, bool IsBranch, uint64_t /*Offset*/, uint64_t /*InstSize*/) { - typedef std::tuple SymbolInfoTy; - typedef std::vector SectionSymbolsTy; + using SymbolInfoTy = std::tuple; + using SectionSymbolsTy = std::vector; if (!IsBranch) { return false; diff --git a/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h b/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h index b39d145e6d2..c487fe9b9db 100644 --- a/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h +++ b/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h @@ -1,4 +1,4 @@ -//===-- AMDGPUDisassembler.hpp - Disassembler for AMDGPU ISA ---*- C++ -*--===// +//===- AMDGPUDisassembler.hpp - Disassembler for AMDGPU ISA -----*- C++ -*-===// // // The LLVM Compiler Infrastructure // @@ -60,10 +60,8 @@ public: MCOperand errOperand(unsigned V, const Twine& ErrMsg) const; - DecodeStatus tryDecodeInst(const uint8_t* Table, - MCInst &MI, - uint64_t Inst, - uint64_t Address) const; + DecodeStatus tryDecodeInst(const uint8_t* Table, MCInst &MI, uint64_t Inst, + uint64_t Address) const; DecodeStatus convertSDWAInst(MCInst &MI) const; diff --git a/lib/Target/AMDGPU/GCNIterativeScheduler.cpp b/lib/Target/AMDGPU/GCNIterativeScheduler.cpp index 2e7641cda37..9e743850f9a 100644 --- a/lib/Target/AMDGPU/GCNIterativeScheduler.cpp +++ b/lib/Target/AMDGPU/GCNIterativeScheduler.cpp @@ -1,4 +1,4 @@ -//===--------------------- GCNIterativeScheduler.cpp - --------------------===// +//===- GCNIterativeScheduler.cpp ------------------------------------------===// // // The LLVM Compiler Infrastructure // @@ -6,23 +6,40 @@ // License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// -// -/// \file -// -//===----------------------------------------------------------------------===// #include "GCNIterativeScheduler.h" +#include "AMDGPUSubtarget.h" +#include "GCNRegPressure.h" #include "GCNSchedStrategy.h" -#include "SIMachineFunctionInfo.h" +#include "llvm/ADT/ArrayRef.h" +#include "llvm/ADT/STLExtras.h" +#include "llvm/ADT/SmallVector.h" +#include "llvm/CodeGen/LiveIntervalAnalysis.h" +#include "llvm/CodeGen/MachineBasicBlock.h" +#include "llvm/CodeGen/MachineFunction.h" +#include "llvm/CodeGen/RegisterPressure.h" +#include "llvm/CodeGen/ScheduleDAG.h" +#include "llvm/Support/Compiler.h" +#include "llvm/Support/Debug.h" +#include "llvm/Support/raw_ostream.h" +#include +#include +#include +#include +#include +#include +#include using namespace llvm; #define DEBUG_TYPE "machine-scheduler" namespace llvm { - std::vector makeMinRegSchedule(ArrayRef TopRoots, - const ScheduleDAG &DAG); -} + +std::vector makeMinRegSchedule(ArrayRef TopRoots, + const ScheduleDAG &DAG); + +} // end namespace llvm // shim accessors for different order containers static inline MachineInstr *getMachineInstr(MachineInstr *MI) { @@ -117,13 +134,13 @@ void GCNIterativeScheduler::printSchedRP(raw_ostream &OS, OS << "RP after: "; After.print(OS, &ST); } - #endif // DAG builder helper class GCNIterativeScheduler::BuildDAG { GCNIterativeScheduler &Sch; - SmallVector TopRoots; + SmallVector TopRoots; + public: BuildDAG(const Region &R, GCNIterativeScheduler &_Sch) : Sch(_Sch) { @@ -135,14 +152,16 @@ public: /*TrackLaneMask*/true); Sch.Topo.InitDAGTopologicalSorting(); - SmallVector BotRoots; + SmallVector BotRoots; Sch.findRootsAndBiasEdges(TopRoots, BotRoots); } + ~BuildDAG() { Sch.BaseClass::exitRegion(); Sch.BaseClass::finishBlock(); } - ArrayRef getTopRoots() const { + + ArrayRef getTopRoots() const { return TopRoots; } }; @@ -152,6 +171,7 @@ class GCNIterativeScheduler::OverrideLegacyStrategy { Region &Rgn; std::unique_ptr SaveSchedImpl; GCNRegPressure SaveMaxRP; + public: OverrideLegacyStrategy(Region &R, MachineSchedStrategy &OverrideStrategy, @@ -165,12 +185,14 @@ public: Sch.BaseClass::startBlock(BB); Sch.BaseClass::enterRegion(BB, R.Begin, R.End, R.NumRegionInstrs); } + ~OverrideLegacyStrategy() { Sch.BaseClass::exitRegion(); Sch.BaseClass::finishBlock(); Sch.SchedImpl.release(); Sch.SchedImpl = std::move(SaveSchedImpl); } + void schedule() { assert(Sch.RegionBegin == Rgn.Begin && Sch.RegionEnd == Rgn.End); DEBUG(dbgs() << "\nScheduling "; @@ -183,6 +205,7 @@ public: Rgn.Begin = Sch.RegionBegin; Rgn.MaxPressure.clear(); } + void restoreOrder() { assert(Sch.RegionBegin == Rgn.Begin && Sch.RegionEnd == Rgn.End); // DAG SUnits are stored using original region's order @@ -192,6 +215,7 @@ public: }; namespace { + // just a stub to make base class happy class SchedStrategyStub : public MachineSchedStrategy { public: @@ -203,7 +227,8 @@ public: void releaseTopNode(SUnit *SU) override {} void releaseBottomNode(SUnit *SU) override {} }; -} // namespace + +} // end anonymous namespace GCNIterativeScheduler::GCNIterativeScheduler(MachineSchedContext *C, StrategyKind S) diff --git a/lib/Target/AMDGPU/GCNIterativeScheduler.h b/lib/Target/AMDGPU/GCNIterativeScheduler.h index df3afce21eb..d002fe66827 100644 --- a/lib/Target/AMDGPU/GCNIterativeScheduler.h +++ b/lib/Target/AMDGPU/GCNIterativeScheduler.h @@ -1,4 +1,4 @@ -//===--------- GCNIterativeScheduler.h - GCN Scheduler -*- C++ -*----------===// +//===- GCNIterativeScheduler.h - GCN Scheduler ------------------*- C++ -*-===// // // The LLVM Compiler Infrastructure // @@ -6,22 +6,28 @@ // License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// -// -/// \file -// -//===----------------------------------------------------------------------===// #ifndef LLVM_LIB_TARGET_AMDGPU_GCNITERATIVESCHEDULER_H #define LLVM_LIB_TARGET_AMDGPU_GCNITERATIVESCHEDULER_H #include "GCNRegPressure.h" - +#include "llvm/ADT/ArrayRef.h" +#include "llvm/CodeGen/MachineBasicBlock.h" #include "llvm/CodeGen/MachineScheduler.h" +#include "llvm/Support/Allocator.h" +#include +#include +#include namespace llvm { +class MachineInstr; +class SUnit; +class raw_ostream; + class GCNIterativeScheduler : public ScheduleDAGMILive { - typedef ScheduleDAGMILive BaseClass; + using BaseClass = ScheduleDAGMILive; + public: enum StrategyKind { SCHEDULE_MINREGONLY, @@ -42,11 +48,10 @@ public: void finalizeSchedule() override; protected: - - typedef ArrayRef ScheduleRef; + using ScheduleRef = ArrayRef; struct TentativeSchedule { - std::vector Schedule; + std::vector Schedule; GCNRegPressure MaxPressure; }; @@ -113,6 +118,6 @@ protected: const GCNRegPressure &After) const; }; -} // End namespace llvm +} // end namespace llvm #endif // LLVM_LIB_TARGET_AMDGPU_GCNITERATIVESCHEDULER_H diff --git a/lib/Target/AMDGPU/GCNRegPressure.cpp b/lib/Target/AMDGPU/GCNRegPressure.cpp index 0384340174f..f8d0acb3df9 100644 --- a/lib/Target/AMDGPU/GCNRegPressure.cpp +++ b/lib/Target/AMDGPU/GCNRegPressure.cpp @@ -1,4 +1,4 @@ -//===------------------------- GCNRegPressure.cpp - -----------------------===// +//===- GCNRegPressure.cpp -------------------------------------------------===// // // The LLVM Compiler Infrastructure // @@ -6,13 +6,26 @@ // License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// -// -/// \file -// -//===----------------------------------------------------------------------===// #include "GCNRegPressure.h" +#include "AMDGPUSubtarget.h" +#include "SIRegisterInfo.h" +#include "llvm/ADT/SmallVector.h" +#include "llvm/CodeGen/LiveInterval.h" +#include "llvm/CodeGen/LiveIntervalAnalysis.h" +#include "llvm/CodeGen/MachineInstr.h" +#include "llvm/CodeGen/MachineOperand.h" +#include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/RegisterPressure.h" +#include "llvm/CodeGen/SlotIndexes.h" +#include "llvm/MC/LaneBitmask.h" +#include "llvm/Support/Compiler.h" +#include "llvm/Support/Debug.h" +#include "llvm/Support/ErrorHandling.h" +#include "llvm/Support/raw_ostream.h" +#include "llvm/Target/TargetRegisterInfo.h" +#include +#include using namespace llvm; @@ -63,7 +76,6 @@ static bool isEqual(const GCNRPTracker::LiveRegSet &S1, } return true; } - #endif /////////////////////////////////////////////////////////////////////////////// @@ -177,7 +189,6 @@ void GCNRegPressure::print(raw_ostream &OS, const SISubtarget *ST) const { } #endif - static LaneBitmask getDefRegMask(const MachineOperand &MO, const MachineRegisterInfo &MRI) { assert(MO.isDef() && MO.isReg() && diff --git a/lib/Target/AMDGPU/GCNRegPressure.h b/lib/Target/AMDGPU/GCNRegPressure.h index 5dfe44053e7..32a199d510c 100644 --- a/lib/Target/AMDGPU/GCNRegPressure.h +++ b/lib/Target/AMDGPU/GCNRegPressure.h @@ -1,4 +1,4 @@ -//===---------------------- GCNRegPressure.h -*- C++ -*--------------------===// +//===- GCNRegPressure.h -----------------------------------------*- C++ -*-===// // // The LLVM Compiler Infrastructure // @@ -6,20 +6,26 @@ // License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// -// -/// \file -// -//===----------------------------------------------------------------------===// #ifndef LLVM_LIB_TARGET_AMDGPU_GCNREGPRESSURE_H #define LLVM_LIB_TARGET_AMDGPU_GCNREGPRESSURE_H #include "AMDGPUSubtarget.h" - +#include "llvm/ADT/DenseMap.h" +#include "llvm/CodeGen/LiveIntervalAnalysis.h" +#include "llvm/CodeGen/MachineBasicBlock.h" +#include "llvm/CodeGen/MachineInstr.h" +#include "llvm/CodeGen/SlotIndexes.h" +#include "llvm/MC/LaneBitmask.h" +#include "llvm/Support/Debug.h" +#include #include namespace llvm { +class MachineRegisterInfo; +class raw_ostream; + struct GCNRegPressure { enum RegKind { SGPR32, @@ -68,7 +74,7 @@ struct GCNRegPressure { return !(*this == O); } - void print(raw_ostream &OS, const SISubtarget *ST=nullptr) const; + void print(raw_ostream &OS, const SISubtarget *ST = nullptr) const; void dump() const { print(dbgs()); } private: @@ -89,7 +95,7 @@ inline GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2) { class GCNRPTracker { public: - typedef DenseMap LiveRegSet; + using LiveRegSet = DenseMap; protected: const LiveIntervals &LIS; @@ -97,7 +103,9 @@ protected: GCNRegPressure CurPressure, MaxPressure; const MachineInstr *LastTrackedMI = nullptr; mutable const MachineRegisterInfo *MRI = nullptr; + GCNRPTracker(const LiveIntervals &LIS_) : LIS(LIS_) {} + public: // live regs for the current state const decltype(LiveRegs) &getLiveRegs() const { return LiveRegs; } @@ -111,9 +119,11 @@ public: MaxPressure.clear(); return Res; } + decltype(LiveRegs) moveLiveRegs() { return std::move(LiveRegs); } + static void printLiveRegs(raw_ostream &OS, const LiveRegSet& LiveRegs, const MachineRegisterInfo &MRI); }; @@ -121,6 +131,7 @@ public: class GCNUpwardRPTracker : public GCNRPTracker { public: GCNUpwardRPTracker(const LiveIntervals &LIS_) : GCNRPTracker(LIS_) {} + // reset tracker to the point just below MI // filling live regs upon this point using LIS void reset(const MachineInstr &MI, const LiveRegSet *LiveRegs = nullptr); @@ -202,6 +213,6 @@ void printLivesAt(SlotIndex SI, const LiveIntervals &LIS, const MachineRegisterInfo &MRI); -} // End namespace llvm +} // end namespace llvm #endif // LLVM_LIB_TARGET_AMDGPU_GCNREGPRESSURE_H diff --git a/lib/Target/AMDGPU/R600ControlFlowFinalizer.cpp b/lib/Target/AMDGPU/R600ControlFlowFinalizer.cpp index 1a11ad35512..be6a45da116 100644 --- a/lib/Target/AMDGPU/R600ControlFlowFinalizer.cpp +++ b/lib/Target/AMDGPU/R600ControlFlowFinalizer.cpp @@ -1,4 +1,4 @@ -//===-- R600ControlFlowFinalizer.cpp - Finalize Control Flow Inst----------===// +//===- R600ControlFlowFinalizer.cpp - Finalize Control Flow Inst ----------===// // // The LLVM Compiler Infrastructure // @@ -9,7 +9,8 @@ // /// \file /// This pass compute turns all control flow pseudo instructions into native one -/// computing their address on the fly ; it also sets STACK_SIZE info. +/// computing their address on the fly; it also sets STACK_SIZE info. +// //===----------------------------------------------------------------------===// #include "AMDGPU.h" @@ -29,13 +30,15 @@ #include "llvm/CodeGen/MachineOperand.h" #include "llvm/IR/CallingConv.h" #include "llvm/IR/DebugLoc.h" +#include "llvm/IR/Function.h" +#include "llvm/Pass.h" +#include "llvm/Support/Compiler.h" #include "llvm/Support/Debug.h" #include "llvm/Support/MathExtras.h" #include "llvm/Support/raw_ostream.h" #include #include #include -#include #include #include #include @@ -47,7 +50,6 @@ using namespace llvm; namespace { struct CFStack { - enum StackItem { ENTRY = 0, SUB_ENTRY = 1, @@ -214,7 +216,7 @@ void CFStack::popLoop() { class R600ControlFlowFinalizer : public MachineFunctionPass { private: - typedef std::pair> ClauseFile; + using ClauseFile = std::pair>; enum ControlFlowInstruction { CF_TC, diff --git a/lib/Target/AMDGPU/R600ExpandSpecialInstrs.cpp b/lib/Target/AMDGPU/R600ExpandSpecialInstrs.cpp index 620e8781a47..ffea231ee4d 100644 --- a/lib/Target/AMDGPU/R600ExpandSpecialInstrs.cpp +++ b/lib/Target/AMDGPU/R600ExpandSpecialInstrs.cpp @@ -1,4 +1,4 @@ -//===-- R600ExpandSpecialInstrs.cpp - Expand special instructions ---------===// +//===- R600ExpandSpecialInstrs.cpp - Expand special instructions ----------===// // // The LLVM Compiler Infrastructure // @@ -18,11 +18,17 @@ #include "AMDGPUSubtarget.h" #include "R600Defines.h" #include "R600InstrInfo.h" -#include "R600MachineFunctionInfo.h" #include "R600RegisterInfo.h" +#include "llvm/CodeGen/MachineBasicBlock.h" +#include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineFunctionPass.h" +#include "llvm/CodeGen/MachineInstr.h" #include "llvm/CodeGen/MachineInstrBuilder.h" -#include "llvm/CodeGen/MachineRegisterInfo.h" +#include "llvm/CodeGen/MachineOperand.h" +#include "llvm/Pass.h" +#include +#include +#include using namespace llvm; @@ -32,7 +38,7 @@ namespace { class R600ExpandSpecialInstrsPass : public MachineFunctionPass { private: - const R600InstrInfo *TII; + const R600InstrInfo *TII = nullptr; void SetFlagInNewMI(MachineInstr *NewMI, const MachineInstr *OldMI, unsigned Op); @@ -40,8 +46,7 @@ private: public: static char ID; - R600ExpandSpecialInstrsPass() : MachineFunctionPass(ID), - TII(nullptr) { } + R600ExpandSpecialInstrsPass() : MachineFunctionPass(ID) {} bool runOnMachineFunction(MachineFunction &MF) override; @@ -50,7 +55,7 @@ public: } }; -} // End anonymous namespace +} // end anonymous namespace INITIALIZE_PASS_BEGIN(R600ExpandSpecialInstrsPass, DEBUG_TYPE, "R600 Expand Special Instrs", false, false) @@ -127,7 +132,6 @@ bool R600ExpandSpecialInstrsPass::runOnMachineFunction(MachineFunction &MF) { continue; } case AMDGPU::DOT_4: { - const R600RegisterInfo &TRI = TII->getRegisterInfo(); unsigned DstReg = MI.getOperand(0).getReg(); diff --git a/lib/Target/AMDGPU/R600OptimizeVectorRegisters.cpp b/lib/Target/AMDGPU/R600OptimizeVectorRegisters.cpp index 402c3f46de1..972e61d376d 100644 --- a/lib/Target/AMDGPU/R600OptimizeVectorRegisters.cpp +++ b/lib/Target/AMDGPU/R600OptimizeVectorRegisters.cpp @@ -1,4 +1,4 @@ -//===--------------------- R600MergeVectorRegisters.cpp -------------------===// +//===- R600MergeVectorRegisters.cpp ---------------------------------------===// // // The LLVM Compiler Infrastructure // @@ -44,7 +44,7 @@ #include "llvm/CodeGen/MachineOperand.h" #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/IR/DebugLoc.h" -#include "llvm/PassAnalysisSupport.h" +#include "llvm/Pass.h" #include "llvm/Support/Debug.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/raw_ostream.h" @@ -98,8 +98,13 @@ public: class R600VectorRegMerger : public MachineFunctionPass { private: + using InstructionSetMap = DenseMap>; + MachineRegisterInfo *MRI; - const R600InstrInfo *TII; + const R600InstrInfo *TII = nullptr; + DenseMap PreviousRegSeq; + InstructionSetMap PreviousRegSeqByReg; + InstructionSetMap PreviousRegSeqByUndefCount; bool canSwizzle(const MachineInstr &MI) const; bool areAllUsesSwizzeable(unsigned Reg) const; @@ -116,16 +121,10 @@ private: void RemoveMI(MachineInstr *); void trackRSI(const RegSeqInfo &RSI); - typedef DenseMap> InstructionSetMap; - DenseMap PreviousRegSeq; - InstructionSetMap PreviousRegSeqByReg; - InstructionSetMap PreviousRegSeqByUndefCount; - public: static char ID; - R600VectorRegMerger() : MachineFunctionPass(ID), - TII(nullptr) { } + R600VectorRegMerger() : MachineFunctionPass(ID) {} void getAnalysisUsage(AnalysisUsage &AU) const override { AU.setPreservesCFG(); @@ -143,7 +142,7 @@ public: bool runOnMachineFunction(MachineFunction &Fn) override; }; -} // end anonymous namespace. +} // end anonymous namespace INITIALIZE_PASS_BEGIN(R600VectorRegMerger, DEBUG_TYPE, "R600 Vector Reg Merger", false, false) diff --git a/lib/Target/AMDGPU/SIMemoryLegalizer.cpp b/lib/Target/AMDGPU/SIMemoryLegalizer.cpp index 48812c84b20..947ca1da78b 100644 --- a/lib/Target/AMDGPU/SIMemoryLegalizer.cpp +++ b/lib/Target/AMDGPU/SIMemoryLegalizer.cpp @@ -1,4 +1,4 @@ -//===--- SIMemoryLegalizer.cpp ----------------------------------*- C++ -*-===// +//===- SIMemoryLegalizer.cpp ----------------------------------------------===// // // The LLVM Compiler Infrastructure // @@ -11,17 +11,33 @@ /// \brief Memory legalizer - implements memory model. More information can be /// found here: /// http://llvm.org/docs/AMDGPUUsage.html#memory-model -/// // //===----------------------------------------------------------------------===// #include "AMDGPU.h" #include "AMDGPUMachineModuleInfo.h" #include "AMDGPUSubtarget.h" +#include "SIDefines.h" +#include "SIInstrInfo.h" #include "Utils/AMDGPUBaseInfo.h" +#include "llvm/ADT/None.h" +#include "llvm/ADT/Optional.h" +#include "llvm/CodeGen/MachineBasicBlock.h" +#include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineInstrBuilder.h" +#include "llvm/CodeGen/MachineMemOperand.h" +#include "llvm/CodeGen/MachineModuleInfo.h" +#include "llvm/CodeGen/MachineOperand.h" +#include "llvm/IR/DebugLoc.h" #include "llvm/IR/DiagnosticInfo.h" +#include "llvm/IR/Function.h" +#include "llvm/IR/LLVMContext.h" +#include "llvm/MC/MCInstrDesc.h" +#include "llvm/Pass.h" +#include "llvm/Support/AtomicOrdering.h" +#include +#include using namespace llvm; using namespace llvm::AMDGPU; @@ -38,7 +54,7 @@ private: AtomicOrdering Ordering = AtomicOrdering::SequentiallyConsistent; AtomicOrdering FailureOrdering = AtomicOrdering::SequentiallyConsistent; - AtomicInfo() {} + AtomicInfo() = default; AtomicInfo(SyncScope::ID SSID, AtomicOrdering Ordering, @@ -55,13 +71,16 @@ private: /// \brief LLVM context. LLVMContext *CTX = nullptr; + /// \brief Machine module info. const AMDGPUMachineModuleInfo *MMI = nullptr; + /// \brief Instruction info. const SIInstrInfo *TII = nullptr; /// \brief Immediate for "vmcnt(0)". unsigned Vmcnt0Immediate = 0; + /// \brief Opcode for cache invalidation instruction (L1). unsigned Wbinvl1Opcode = 0; @@ -134,8 +153,7 @@ private: public: static char ID; - SIMemoryLegalizer() - : MachineFunctionPass(ID) {} + SIMemoryLegalizer() : MachineFunctionPass(ID) {} void getAnalysisUsage(AnalysisUsage &AU) const override { AU.setPreservesCFG(); diff --git a/lib/Target/AMDGPU/Utils/AMDKernelCodeTUtils.cpp b/lib/Target/AMDGPU/Utils/AMDKernelCodeTUtils.cpp index 0333b0a14d2..20059f4a1ed 100644 --- a/lib/Target/AMDGPU/Utils/AMDKernelCodeTUtils.cpp +++ b/lib/Target/AMDGPU/Utils/AMDKernelCodeTUtils.cpp @@ -1,4 +1,4 @@ -//===--------------------AMDKernelCodeTUtils.cpp --------------------------===// +//===- AMDKernelCodeTUtils.cpp --------------------------------------------===// // // The LLVM Compiler Infrastructure // @@ -7,17 +7,21 @@ // //===----------------------------------------------------------------------===// // -//===----------------------------------------------------------------------===// -// /// \file - utility functions to parse/print amd_kernel_code_t structure // //===----------------------------------------------------------------------===// #include "AMDKernelCodeTUtils.h" #include "SIDefines.h" -#include -#include -#include +#include "llvm/ADT/ArrayRef.h" +#include "llvm/ADT/StringMap.h" +#include "llvm/ADT/StringRef.h" +#include "llvm/MC/MCParser/MCAsmLexer.h" +#include "llvm/MC/MCParser/MCAsmParser.h" +#include "llvm/Support/raw_ostream.h" +#include +#include +#include using namespace llvm; @@ -62,7 +66,6 @@ static StringRef get_amd_kernel_code_t_FieldName(int index) { return get_amd_kernel_code_t_FldNames()[index + 1]; } - // Field printing static raw_ostream &printName(raw_ostream &OS, StringRef Name) { @@ -82,9 +85,7 @@ static void printBitField(StringRef Name, const amd_kernel_code_t &c, printName(OS, Name) << (int)((c.*ptr >> shift) & Mask); } -typedef void(*PrintFx)(StringRef, - const amd_kernel_code_t &, - raw_ostream &); +using PrintFx = void(*)(StringRef, const amd_kernel_code_t &, raw_ostream &); static ArrayRef getPrinterTable() { static const PrintFx Table[] = { @@ -114,7 +115,6 @@ void llvm::dumpAmdKernelCode(const amd_kernel_code_t *C, } } - // Field parsing static bool expectAbsExpression(MCAsmParser &MCParser, int64_t &Value, raw_ostream& Err) { @@ -154,9 +154,8 @@ static bool parseBitField(amd_kernel_code_t &C, MCAsmParser &MCParser, return true; } -typedef bool(*ParseFx)(amd_kernel_code_t &, - MCAsmParser &MCParser, - raw_ostream &Err); +using ParseFx = bool(*)(amd_kernel_code_t &, MCAsmParser &MCParser, + raw_ostream &Err); static ArrayRef getParserTable() { static const ParseFx Table[] = { diff --git a/lib/Target/AMDGPU/Utils/AMDKernelCodeTUtils.h b/lib/Target/AMDGPU/Utils/AMDKernelCodeTUtils.h index d9edca7a82a..ef9f9bdb6bc 100644 --- a/lib/Target/AMDGPU/Utils/AMDKernelCodeTUtils.h +++ b/lib/Target/AMDGPU/Utils/AMDKernelCodeTUtils.h @@ -1,4 +1,4 @@ -//===- AMDGPUKernelCodeTUtils.h - helpers for amd_kernel_code_t *- C++ -*-===// +//===- AMDGPUKernelCodeTUtils.h - helpers for amd_kernel_code_t -*- C++ -*-===// // // The LLVM Compiler Infrastructure // @@ -6,34 +6,31 @@ // License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// +// /// \file AMDKernelCodeTUtils.h +// //===----------------------------------------------------------------------===// -#ifndef AMDKERNELCODETUTILS_H -#define AMDKERNELCODETUTILS_H +#ifndef LLVM_LIB_TARGET_AMDGPU_UTILS_AMDKERNELCODETUTILS_H +#define LLVM_LIB_TARGET_AMDGPU_UTILS_AMDKERNELCODETUTILS_H #include "AMDKernelCodeT.h" namespace llvm { -class MCAsmLexer; class MCAsmParser; class raw_ostream; class StringRef; -void printAmdKernelCodeField(const amd_kernel_code_t &C, - int FldIndex, - raw_ostream &OS); +void printAmdKernelCodeField(const amd_kernel_code_t &C, int FldIndex, + raw_ostream &OS); -void dumpAmdKernelCode(const amd_kernel_code_t *C, - raw_ostream &OS, - const char *tab); +void dumpAmdKernelCode(const amd_kernel_code_t *C, raw_ostream &OS, + const char *tab); -bool parseAmdKernelCodeField(StringRef ID, - MCAsmParser &Parser, - amd_kernel_code_t &C, - raw_ostream &Err); +bool parseAmdKernelCodeField(StringRef ID, MCAsmParser &Parser, + amd_kernel_code_t &C, raw_ostream &Err); -} +} // end namespace llvm -#endif // AMDKERNELCODETUTILS_H +#endif // LLVM_LIB_TARGET_AMDGPU_UTILS_AMDKERNELCODETUTILS_H -- 2.50.1