From 7465dfa45673d855127fc8efe09cf201343784a5 Mon Sep 17 00:00:00 2001 From: Simon Atanasyan Date: Thu, 7 Sep 2017 12:54:26 +0000 Subject: [PATCH] [mips] Use RegisterMCAsmBackend to register all MIPS asm backends. NFC This change converts the `MipsAsmBackend` constructor to the "standard" form. It makes possible to use `RegisterMCAsmBackend` for the backends registrations. Now we pass `Triple` instance to the `MipsAsmBackend` ctor and deduce all required options like endianness and bitness from the triple. We still need to implement explicit ABI checking for providing correct options to backends. Differential revision: https://reviews.llvm.org/D37519 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312720 91177308-0d34-0410-b5e6-96231b3b80d8 --- .../Mips/MCTargetDesc/MipsAsmBackend.cpp | 35 +------------------ lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h | 12 +++---- .../Mips/MCTargetDesc/MipsELFObjectWriter.cpp | 27 +++++++------- .../Mips/MCTargetDesc/MipsMCTargetDesc.cpp | 14 +++----- .../Mips/MCTargetDesc/MipsMCTargetDesc.h | 21 ++--------- 5 files changed, 28 insertions(+), 81 deletions(-) diff --git a/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp b/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp index a1ed0ea4d7f..62715600583 100644 --- a/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp +++ b/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp @@ -211,8 +211,7 @@ static unsigned adjustFixupValue(const MCFixup &Fixup, uint64_t Value, MCObjectWriter * MipsAsmBackend::createObjectWriter(raw_pwrite_stream &OS) const { - return createMipsELFObjectWriter(OS, - MCELFObjectTargetWriter::getOSABI(OSType), IsLittle, Is64Bit); + return createMipsELFObjectWriter(OS, TheTriple); } // Little-endian fixup data byte ordering: @@ -474,35 +473,3 @@ bool MipsAsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const { OW->WriteZeros(Count); return true; } - -// MCAsmBackend -MCAsmBackend *llvm::createMipsAsmBackendEL32(const Target &T, - const MCRegisterInfo &MRI, - const Triple &TT, StringRef CPU, - const MCTargetOptions &Options) { - return new MipsAsmBackend(T, TT.getOS(), /*IsLittle*/ true, - /*Is64Bit*/ false); -} - -MCAsmBackend *llvm::createMipsAsmBackendEB32(const Target &T, - const MCRegisterInfo &MRI, - const Triple &TT, StringRef CPU, - const MCTargetOptions &Options) { - return new MipsAsmBackend(T, TT.getOS(), /*IsLittle*/ false, - /*Is64Bit*/ false); -} - -MCAsmBackend *llvm::createMipsAsmBackendEL64(const Target &T, - const MCRegisterInfo &MRI, - const Triple &TT, StringRef CPU, - const MCTargetOptions &Options) { - return new MipsAsmBackend(T, TT.getOS(), /*IsLittle*/ true, /*Is64Bit*/ true); -} - -MCAsmBackend *llvm::createMipsAsmBackendEB64(const Target &T, - const MCRegisterInfo &MRI, - const Triple &TT, StringRef CPU, - const MCTargetOptions &Options) { - return new MipsAsmBackend(T, TT.getOS(), /*IsLittle*/ false, - /*Is64Bit*/ true); -} diff --git a/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h b/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h index 8ebde3b9b7a..e2305bd27f0 100644 --- a/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h +++ b/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h @@ -23,18 +23,18 @@ namespace llvm { class MCAssembler; struct MCFixupKindInfo; -class Target; class MCObjectWriter; +class MCRegisterInfo; +class Target; class MipsAsmBackend : public MCAsmBackend { - Triple::OSType OSType; + Triple TheTriple; bool IsLittle; // Big or little endian - bool Is64Bit; // 32 or 64 bit words public: - MipsAsmBackend(const Target &T, Triple::OSType OSType, bool IsLittle, - bool Is64Bit) - : MCAsmBackend(), OSType(OSType), IsLittle(IsLittle), Is64Bit(Is64Bit) {} + MipsAsmBackend(const Target &T, const MCRegisterInfo &MRI, const Triple &TT, + StringRef CPU) + : TheTriple(TT), IsLittle(TT.isLittleEndian()) {} MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override; diff --git a/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp b/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp index d116ac3471b..469e598f4b3 100644 --- a/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp +++ b/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp @@ -55,7 +55,7 @@ raw_ostream &operator<<(raw_ostream &OS, const MipsRelocationEntry &RHS) { class MipsELFObjectWriter : public MCELFObjectTargetWriter { public: - MipsELFObjectWriter(bool _is64Bit, uint8_t OSABI, bool _isN64, + MipsELFObjectWriter(uint8_t OSABI, bool HasRelocationAddend, bool IsN64, bool IsLittleEndian); ~MipsELFObjectWriter() override = default; @@ -209,11 +209,11 @@ static void dumpRelocs(const char *Prefix, const Container &Relocs) { } #endif -MipsELFObjectWriter::MipsELFObjectWriter(bool _is64Bit, uint8_t OSABI, - bool _isN64, bool IsLittleEndian) - : MCELFObjectTargetWriter(_is64Bit, OSABI, ELF::EM_MIPS, - /*HasRelocationAddend*/ _isN64, - /*IsN64*/ _isN64) {} +MipsELFObjectWriter::MipsELFObjectWriter(uint8_t OSABI, + bool HasRelocationAddend, bool IsN64, + bool IsLittleEndian) + : MCELFObjectTargetWriter(IsN64, OSABI, ELF::EM_MIPS, HasRelocationAddend, + IsN64) {} unsigned MipsELFObjectWriter::getRelocType(MCContext &Ctx, const MCValue &Target, @@ -657,10 +657,13 @@ bool MipsELFObjectWriter::needsRelocateWithSymbol(const MCSymbol &Sym, } MCObjectWriter *llvm::createMipsELFObjectWriter(raw_pwrite_stream &OS, - uint8_t OSABI, - bool IsLittleEndian, - bool Is64Bit) { - MCELFObjectTargetWriter *MOTW = - new MipsELFObjectWriter(Is64Bit, OSABI, Is64Bit, IsLittleEndian); - return createELFObjectWriter(MOTW, OS, IsLittleEndian); + const Triple &TT) { + uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS()); + // FIXME: We need to check an actual ABI. mips64/mips64el do not + // always imply the N64 ABI and RELA relocation's format. + bool IsN64 = TT.isArch64Bit(); + bool HasRelocationAddend = IsN64; + auto *MOTW = new MipsELFObjectWriter(OSABI, HasRelocationAddend, IsN64, + TT.isLittleEndian()); + return createELFObjectWriter(MOTW, OS, TT.isLittleEndian()); } diff --git a/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp b/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp index 56fe1857211..7609ff2d69e 100644 --- a/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp +++ b/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp @@ -13,6 +13,7 @@ #include "MipsMCTargetDesc.h" #include "InstPrinter/MipsInstPrinter.h" +#include "MipsAsmBackend.h" #include "MipsELFStreamer.h" #include "MipsMCAsmInfo.h" #include "MipsMCNaCl.h" @@ -180,6 +181,9 @@ extern "C" void LLVMInitializeMipsTargetMC() { TargetRegistry::RegisterObjectTargetStreamer( *T, createMipsObjectTargetStreamer); + + // Register the asm backend. + RegisterMCAsmBackend Y(*T); } // Register the MC Code Emitter @@ -188,14 +192,4 @@ extern "C" void LLVMInitializeMipsTargetMC() { for (Target *T : {&getTheMipselTarget(), &getTheMips64elTarget()}) TargetRegistry::RegisterMCCodeEmitter(*T, createMipsMCCodeEmitterEL); - - // Register the asm backend. - TargetRegistry::RegisterMCAsmBackend(getTheMipsTarget(), - createMipsAsmBackendEB32); - TargetRegistry::RegisterMCAsmBackend(getTheMipselTarget(), - createMipsAsmBackendEL32); - TargetRegistry::RegisterMCAsmBackend(getTheMips64Target(), - createMipsAsmBackendEB64); - TargetRegistry::RegisterMCAsmBackend(getTheMips64elTarget(), - createMipsAsmBackendEL64); } diff --git a/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h b/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h index b28681f42eb..c95efd6cd4b 100644 --- a/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h +++ b/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h @@ -43,25 +43,8 @@ MCCodeEmitter *createMipsMCCodeEmitterEL(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx); -MCAsmBackend *createMipsAsmBackendEB32(const Target &T, - const MCRegisterInfo &MRI, - const Triple &TT, StringRef CPU, - const MCTargetOptions &Options); -MCAsmBackend *createMipsAsmBackendEL32(const Target &T, - const MCRegisterInfo &MRI, - const Triple &TT, StringRef CPU, - const MCTargetOptions &Options); -MCAsmBackend *createMipsAsmBackendEB64(const Target &T, - const MCRegisterInfo &MRI, - const Triple &TT, StringRef CPU, - const MCTargetOptions &Options); -MCAsmBackend *createMipsAsmBackendEL64(const Target &T, - const MCRegisterInfo &MRI, - const Triple &TT, StringRef CPU, - const MCTargetOptions &Options); - -MCObjectWriter *createMipsELFObjectWriter(raw_pwrite_stream &OS, uint8_t OSABI, - bool IsLittleEndian, bool Is64Bit); +MCObjectWriter *createMipsELFObjectWriter(raw_pwrite_stream &OS, + const Triple &TT); namespace MIPS_MC { StringRef selectMipsCPU(const Triple &TT, StringRef CPU); -- 2.40.0